ICS1523
Pin Descriptions
PIN NO.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
P I N NA M E
VDDD
VSSD
S DA
SCL
PDEN
EXTFB
HSYNC
EXTFIL
XFILRET
V D DA
VSSA
OSC
I
2
CADR
LOCK/REF
(SSTL)
FUNC (SSTL)
CLK/2 (SSTL)
CLK (SSTL)
VDDQ
VSSQ
CLK– (PECL)
CLK+ (PECL)
CLK/2– (PECL)
CLK/2+ (PECL)
IREF
TYPE
PWR
PWR
IN/OUT
IN
IN
IN
IN
IN
IN
PWR
PWR
IN
IN
OUT
OUT
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
IN
DESCRIPTION
Digital supply
Digital ground
Serial data
Serial clock
PFD enable
External feedback in
Horizontal sync
External filter
External filter return
Analog supply
Analog ground
Oscillator
I
2
C address
Lock indicator/reference
Function output
P i xe l c l o c k / 2 o u t
P i xe l c l o c k o u t
Output driver supply
Output driver ground
P i xe l c l o c k o u t
P i xe l c l o c k o u t
P i xe l c l o c k / 2 o u t
P i xe l c l o c k / 2 o u t
Reference current
I
2
C-bus
1
I
2
C-bus
1
S u s p e n d s c h a rg e p u m p
1
External divider input to P F D
1
Clock input to PLL
1
External PLL loop filter
External PLL loop filter return
3.3V for analog circuitry
Ground for analog circuitry
Input from crystal oscillator package
1 ,
Chip I
2
C address select
Low = 4Dh read, 4Ch write
High = 4Fh read, 4Eh write
Displays PLL or DPA lock or REF input
SSTL_3 selectable HSYNC output
SSTL_3 driver to ADC deMUX input
SSTL_3 driver to ADC
3.3V to output drivers
Ground for output drivers
Inverted PECL driver to ADC. Open drain.
PECL driver to ADC. Open drain.
Inverted PECL driver to ADC deMUX input.
Open drain.
PECL driver to ADC deMUX input. Open drain.
Reference current for PECL outputs
2
COMMENTS
3.3V to digital sections
Notes:
1. These LVTTL inputs are 5 V-tolerant.
2. Connect to ground if unused.
4
ICS [ INTEGRATED CIRCUIT SYSTEMS ]
