ICS1523
Overview
The ICS1523 addresses stringent graphics system line-locked
and genlocked applications and provides the clock signals
required by high-performance video analog-to-digital convert-
ers. Included are a phase-locked loop (PLL) with a 500-MHz
voltage controlled oscillator (VCO), a Dynamic Phase Adjust to
provide a user-programmed pixel clock delay, the means for
deMUXing multiplexed ADCs, and both balanced-program-
mable (PECL) and single-ended (SSTL_3) high-speed clock
outputs.
Phase-Locked Loop
The phase-locked loop is optimized for line-locked applica-
tions, for which the inputs are horizontal sync signals. A
high-performance Schmitt trigger preconditions the HSYNC
input, whose pulses can be degraded if they are from a remote
source. This preconditioned HSYNC signal is provided as a
clean reference signal with a short transition time. (In contrast,
the signal that a typical PC graphics card provides has a transi-
tion time of tens of nanoseconds.)
A second high-frequency input such as a crystal oscillator and
a 7-bit programmable divider can be selected. This selection al-
lows the loop to operate from a local source and is also useful
for evaluating intrinsic jitter.
A 12-bit programmable feedback divider completes the loop.
Designers can substitute an external divider.
Either the conditioned HSYNC input or the loop output (recov-
ered HSYNC) is available at the FUNC pin, aligned to the edge
of the pixel clock.
Automatic Power-On Reset Detection
The ICS1523 has automatic power-on reset detection circuitry
and it resets itself if the supply voltage drops below threshold
values. No external connection to a reset signal is required.
Dynamic Phase Adjust
The Dynamic Phase Adjust allows addition of a program-
mable delay to the pixel clock output, relative to the recovered
HSYNC signal. The ability to add delays is particularly useful
when multiple video sources must be synchronized. A delay of
up to one pixel clock period is selectable in the following
increments:
1/64 period for pixel clock rates to 40 MHz
1/32 period for pixel clock rates to 80 MHz
1/16 period for pixel clock rates to 160 MHz
Output Drivers and Logic Inputs
The ICS1523 utilizes low-voltage TTL (LVTTL) inputs as well
as SSTL_3 (EIA/JESD8-8) and low-voltage PECL (pseudo-
ECL) outputs, operating at 3.3-V supply voltage. The LVTTL
inputs are 5 V-tolerant. The SSTL_3 and differential PECL out-
put drivers drive resistive terminations or transmission lines.
At lower clock frequencies, the SSTL_3 outputs can be oper-
ated unterminated.
I
2
C-bus Serial Interface
The ICS1523 utilizes the industry-standard I
2
C-bus
serial in-
terface. The interface uses 12 registers: one write-only, eight
read/write, and three read-only. Two ICS1523 devices can be
addressed, according to the state of the I
2
CADR pin. When
the pin is low, the read address is 4Dh, and the write address is
4Ch. When the pin is high, the read address is 4Fh, and the
write address is 4Eh. The I
2
C-bus serial interface can run at ei-
ther low speed (100 kHz) or high speed (400 kHz) and provides
5V-tolerant input.
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