IC61LV6432
WRITE CYCLE TIMING
t
KC
CLK
t
KH
tKL
ADSP is blocked by CE1 inactive
ADSC initiate Write
t
SS
tSH
ADSP
ADSC
t
AVH
t
AVS
ADV must be inactive for ADSP Write
ADV
t
AS
tAH
A15-A0
WR1
WR2
WR3
t
t
WS
WS
t
t
WH
WH
GW
BWE
t
WS
t
WH
t
WS
tWH
BW4-BW1
WR1
WR2
CE1 Masks ADSP
WR3
t
CES
tCEH
CE1
CE2
CE3
t
t
CES
CES
t
CEH
CEH
Unselected with CE2
CE2 and CE3 only sampled with ADSP or ADSC
t
OE
DATAOUT
DATAIN
High-Z
t
DS
tDH
BW4-BW1 only are applied to first cycle of WR2
2a 2b 2c 2d
High-Z
3a
1a
Burst Write
Single Write
Write
Unselected
Integrated Circuit Solution Inc.
13
SSR005-0A 02/02/2004