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IC61LV6432-7TQ 参数 Datasheet PDF下载

IC61LV6432-7TQ图片预览
型号: IC61LV6432-7TQ
PDF下载: 下载PDF文件 查看货源
内容描述: 64K ×32流水线同步。 SRAM [64K x 32 Pipelined Sync. SRAM]
分类和应用: 静态存储器
文件页数/大小: 21 页 / 207 K
品牌: ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
 浏览型号IC61LV6432-7TQ的Datasheet PDF文件第8页浏览型号IC61LV6432-7TQ的Datasheet PDF文件第9页浏览型号IC61LV6432-7TQ的Datasheet PDF文件第10页浏览型号IC61LV6432-7TQ的Datasheet PDF文件第11页浏览型号IC61LV6432-7TQ的Datasheet PDF文件第13页浏览型号IC61LV6432-7TQ的Datasheet PDF文件第14页浏览型号IC61LV6432-7TQ的Datasheet PDF文件第15页浏览型号IC61LV6432-7TQ的Datasheet PDF文件第16页  
IC61LV6432  
WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)  
-166  
-133  
-117  
Symbol  
tKC  
Parameter  
Cycle Time  
Clock High Time  
Clock Low Time  
Address Setup Time  
Address Status Setup Time  
Write Setup Time  
Data In Setup Time  
Chip Enable Setup Time  
Address Advance Setup Time  
Address Hold Time  
Address Status Hold Time  
Data In Hold Time  
Min. Max. Min. Max. Min. Max.  
Unit  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
6
7.5  
2.8  
2.8  
2.5  
2.5  
2.5  
2.5  
2.5  
2.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
30  
8.5  
3
tKH  
2.4  
2.4  
2.5  
2.5  
2.5  
2.5  
2.5  
2.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
25  
tKL  
3
tAS  
2.5  
2.5  
2.5  
2.5  
2.5  
2.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
35  
tSS  
tWS  
tDS  
tCES  
tAVS  
tAH  
tSH  
tDH  
tWH  
tCEH  
tAVH  
Write Hold Time  
Chip Enable Hold Time  
Address Advance Hold Time  
ConfigurationSetup  
(2)  
tCFG  
-5  
-6  
-7  
-8  
Symbol  
tKC  
Parameter  
Cycle Time  
Clock High Time  
Clock Low Time  
Address Setup Time  
Address Status Setup Time  
Write Setup Time  
Data In Setup Time  
Chip Enable Setup Time  
Address Advance Setup Time  
Address Hold Time  
Address Status Hold Time  
Data In Hold Time  
Min. Max. Min. Max. Min. Max. Min. Max.  
Unit  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
10  
3.5  
3.5  
2.5  
2.5  
2.5  
2.5  
2.5  
2.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
35  
12  
4
4
13  
6
6
15  
6
6
tKH  
tKL  
tAS  
2.5  
2.5  
2.5  
2.5  
2.5  
2.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
45  
2.5  
2.5  
2.5  
2.5  
2.5  
2.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
52  
2.5  
2.5  
2.5  
2.5  
2.5  
2.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
60  
tSS  
tWS  
tDS  
tCES  
tAVS  
tAH  
tSH  
tDH  
tWH  
tCEH  
tAVH  
Write Hold Time  
Chip Enable Hold Time  
Address Advance Hold Time  
Configuration Setup  
(2)  
tCFG  
Note:  
1. ADVANCE INFORMATION ONLY.  
2. Configuration signal MODE is static and must not change during normal operation.  
12  
Integrated Circuit Solution Inc.  
SSR005-0A 002/02/2004