Integrated
Circuit
Systems, Inc.
ICS85301
2:1
D
IFFERENTIAL
-
TO
-LVPECL M
ULTIPLEXER
Test Conditions
PCLK0, nPCLK0,
PCLK1, nPCLK1
PCLK0, PCLK1
nPCLK0, nPCLK1
V
CC
= V
IN
= 2.625V
V
CC
= 2.625V, V
IN
= 0V
V
CC
= 2.625V, V
IN
= 0V
-10
-150
150
1.2
1.25
0.48
0.935
1200
2.5
1.705
1.005
1.305
Minimum
Typical
Maximum
150
Units
µA
µA
µA
mV
V
V
V
V
T
ABLE
4E. LVPECL DC C
HARACTERISTICS
,
V
CC
= 2.5V ± 5%, T
A
= -40°C
TO
85°C
Symbol Parameter
Input High
I
IH
Current
I
IL
V
PP
V
CMR
V
OH
V
OL
V
BB
Input Low Current
Peak-to-Peak Input Voltage
Common Mode Input Voltage; NOTE 1, 2
Output High Voltage; NOTE 3
Output Low Voltage; NOTE 3
Bias Voltage
NOTE 1: Common mode voltage is defined as V
IH
.
NOTE 2: For single ended applications
,
the maximum input voltage for PCLKx, nPCLKx is V
CC
+ 0.3V.
NOTE 3: Outputs terminated with 50
Ω
to V
CC
- 2V. .
T
ABLE
5A. AC C
HARACTERISTICS
,
V
CC
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
f
MAX
t
PD
t
sk(pp)
t
sk(i)
t
jit
t
R
/ t
F
odc
MUX_
ISOL
Parameter
Output Frequency
Propagation Delay; NOTE 1
Par t-to-Par t Skew; NOTE 2, 3
Input Skew
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section
Output Rise/Fall Time
Output Duty Cycle
MUX Isolation
f = 622MHz
622MHz (Integration Range:
12KHz - 20MHz)
20% to 80%
240
Test Conditions
Minimum
Typical
Maximum
3
490
150
25
0.009
100
48
-55
200
52
Units
GHz
ps
ps
ps
ps
ps
%
dBm
All parameters measured at f
≤
1.7GHz unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
T
ABLE
5B. AC C
HARACTERISTICS
,
V
CC
= 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
f
MAX
t
PD
t
sk(pp)
t
sk(i)
t
jit
t
R
/ t
F
odc
MUX_
ISOL
85301AK
Parameter
Output Frequency
Propagation Delay; NOTE 1
Par t-to-Par t Skew; NOTE 2, 3
Input Skew
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section
Output Rise/Fall Time
Output Duty Cycle
MUX Isolation
Test Conditions
Minimum
240
Typical
Maximum
3
490
150
25
Units
GHz
ps
ps
ps
ps
622MHz (Integration Range:
12KHz - 20MHz)
20% to 80%
f = 622MHz
0.009
100
47
-55
200
53
ps
%
dBm
For notes, see Table 5A above.
www.icst.com/products/hiperclocks.html
4
REV. A JANUARY 16, 2006
ICS [ INTEGRATED CIRCUIT SYSTEMS ]
