ICS85301
2:1
DIFFERENTIAL-TO-LVPECL MULTIPLEXER
Integrated
Circuit
Systems, Inc.
TABLE 4E. LVPECL DC CHARACTERISTICS, VCC = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
VCC = VIN = 2.625V
VCC = 2.625V, VIN = 0V
Minimum Typical Maximum Units
Input High
Current
PCLK0, nPCLK0,
PCLK1, nPCLK1
IIH
150
µA
PCLK0, PCLK1
-10
-150
150
µA
µA
mV
V
IIL
Input Low Current
nPCLK0, nPCLK1
VCC = 2.625V, VIN = 0V
VPP
VCMR
VOH
VOL
VBB
Peak-to-Peak Input Voltage
1200
2.5
Common Mode Input Voltage; NOTE 1, 2
Output High Voltage; NOTE 3
Output Low Voltage; NOTE 3
Bias Voltage
1.2
1.25
0.48
0.935
1.705
1.005
1.305
V
V
V
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2: For single ended applications, the maximum input voltage for PCLKx, nPCLKx is VCC + 0.3V.
NOTE 3: Outputs terminated with 50Ω to VCC - 2V. .
TABLE 5A. AC CHARACTERISTICS, VCC = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol
fMAX
Parameter
Test Conditions
Minimum Typical Maximum Units
Output Frequency
Propagation Delay; NOTE 1
Part-to-Part Skew; NOTE 2, 3
Input Skew
3
GHz
ps
tPD
240
490
150
25
tsk(pp)
tsk(i)
ps
ps
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section
622MHz (Integration Range:
12KHz - 20MHz)
tjit
0.009
-55
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20ꢀ to 80ꢀ
100
48
200
52
ps
ꢀ
MUX_ISOL MUX Isolation
f = 622MHz
dBm
All parameters measured at f ≤ 1.7GHz unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 5B. AC CHARACTERISTICS, VCC = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol
fMAX
Parameter
Test Conditions
Minimum Typical Maximum Units
Output Frequency
Propagation Delay; NOTE 1
Part-to-Part Skew; NOTE 2, 3
Input Skew
3
GHz
ps
tPD
240
490
150
25
tsk(pp)
tsk(i)
ps
ps
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section
622MHz (Integration Range:
12KHz - 20MHz)
tjit
0.009
-55
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20ꢀ to 80ꢀ
100
47
200
53
ps
ꢀ
MUX_ISOL MUX Isolation
f = 622MHz
dBm
For notes, see Table 5A above.
85301AK
www.icst.com/products/hiperclocks.html
REV.A JANUARY 16, 2006
4
ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
