ICS85301
2:1
DIFFERENTIAL-TO-LVPECL MULTIPLEXER
Integrated
Circuit
Systems, Inc.
LVPECL CLOCK INPUT INTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other gested here are examples only. If the driver is from another
differential signals. Both VSWING and VOH must meet the VPP vendor, use their termination recommendation. Please con-
and VCMR input requirements. Figures 2A to 2F show inter- sult with the vendor of the driver component to confirm the
face examples for the HiPerClockS PCLK/nPCLK input driven driver termination requirements.
by the most common driver types. The input interfaces sug-
3.3V
3.3V
3.3V
3.3V
3.3V
R1
50
R2
50
Zo = 50 Ohm
Zo = 50 Ohm
CML
Zo = 50 Ohm
Zo = 50 Ohm
PCLK
PCLK
R1
100
nPCLK
nPCLK
HiPerClockS
HiPerClockS
PCLK/nPCLK
PCLK/nPCLK
CML Built-In Pullup
FIGURE 2A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY AN OPEN COLLECTOR CML DRIVER
FIGURE 2B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A BUILT-IN PULLUP CML DRIVER
3.3V
3.3V
3.3V
3.3V
3.3V
R3
R4
125
125
C1
Zo = 50 Ohm
Zo = 50 Ohm
3.3V LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
PCLK
VBB
PCLK
C2
nPCLK
nPCLK
HiPerClockS
Input
PCLK/nPCLK
LVPECL
R5
100 - 200
R6
100 - 200
R1
50
R2
50
R1
84
R2
84
FIGURE 2C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER
FIGURE 2D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER WITH AC COUPLE
2.5V
3.3V
3.3V
3.3V
2.5V
Zo = 50 Ohm
R3
R4
120
120
C1
LVDS
SSTL
Zo = 60 Ohm
Zo = 60 Ohm
PCLK
PCLK
R5
100
VBB
C2
nPCLK
nPCLK
Zo = 50 Ohm
HiPerClockS
PCLK/nPCLK
PCLK/nPCLK
R1
1K
R2
1K
R1
120
R2
120
FIGURE 2E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY AN SSTL DRIVER
FIGURE 2F. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVDS DRIVER
85301AK
www.icst.com/products/hiperclocks.html
REV.A JANUARY 16, 2006
9
ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
