Integrated
Circuit
Systems, Inc.
ICS85301
2:1
D
IFFERENTIAL
-
TO
-LVPECL M
ULTIPLEXER
Type
Description
Non-inver ting differential LVPECL clock input.
Inver ting differential LVPECL clock input. V
CC
/2 default when left floating.
Non-inver ting differential LVPECL clock input.
Inver ting differential LVPECL clock input. V
CC
/2 default when left floating.
Bias voltage.
No connect.
Clock select input. When HIGH, selects PCLK1, nPCLK1 inputs.
When LOW, selects PCLK0, nPCLK0 inputs.
LVCMOS / LVTTL interface levels.
Positive supply pins.
Negative supply pins.
Differential output pair. LVPECL interface levels.
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2
3
4
5
7, 16
6
8 , 13
9, 12, 14, 15
10, 11
Name
PCLK0
nPCLK0
PCLK1
nPCLK1
V
BB
nc
CLK_SEL
V
CC
V
EE
nQ, Q
Input
Input
Input
Input
Output
Unused
Input
Power
Power
Output
Pulldown
Pulldown
Pullup/
Pulldown
Pulldown
Pullup/
Pulldown
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
1
37
37
Maximum
Units
pF
kΩ
kΩ
T
ABLE
3. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
Input
CLK_SEL
0
1
Input Selected
PCLK
PCLK0, nPCLK0
PCLK1, nPCLK1
85301AK
www.icst.com/products/hiperclocks.html
2
REV. A JANUARY 16, 2006
ICS [ INTEGRATED CIRCUIT SYSTEMS ]
