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301A 参数 Datasheet PDF下载

301A图片预览
型号: 301A
PDF下载: 下载PDF文件 查看货源
内容描述: 2 : 1差分至LVPECL多路复用器 [2:1 DIFFERENTIAL-TO-LVPECL MULTIPLEXER]
分类和应用: 复用器
文件页数/大小: 19 页 / 299 K
品牌: ICS [ INTEGRATED CIRCUIT SYSTEMS ]
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Integrated
Circuit
Systems, Inc.
ICS85301
2:1
D
IFFERENTIAL
-
TO
-LVPECL M
ULTIPLEXER
F
EATURES
2:1 LVPECL MUX
One LVPECL output
Two differential clock inputs can accept: LVPECL, LVDS,
CML
Maximum input/output frequency: 3GHz
Translates LVCMOS/LVTTL input signals to LVPECL levels
by using a resistor bias network on nPCLK0, nPCLK0
Propagation delay: 490ps (maximum)
Part-to-part skew: 150ps (maximum)
Additive phase jitter, RMS: 0.009ps (typical)
Full 3.3V or 2.5V operating supply
-40°C to 85°C ambient operating temperature
Available in both standard and lead-free RoHS compliant
packages
G
ENERAL
D
ESCRIPTION
The ICS85301 is a high performance 2:1 Differ-
ential-to-LVPECL Multiplexer and a member of the
HiPerClockS™
HiPerClockS™ family of High Performance Clock
Solutions from ICS. The ICS85301 can also per-
form differential translation because the differ-
ential inputs accept LVPECL, CML as well as LVDS levels.
The ICS85301 is packaged in a small 3mm x 3mm
16 VFQFN package, making it ideal for use on space con-
strained boards.
IC
S
B
LOCK
D
IAGRAM
PCLK0
nPCLK0
PCLK1
nPCLK1
0
Q
nQ
1
P
IN
A
SSIGNMENT
PCLK0 1
nPCLK0 2
PCLK1 3
nPCLK1 4
5
V
BB
16 15 14 13
12
11
10
9
6
CLK_SEL
V
CC
V
EE
V
EE
nc
V
EE
Q
nQ
V
EE
7
nc
8
V
CC
CLK_SEL
V
BB
ICS85301
16-Lead VFQFN
3mm x 3mm x 0.95 package body
K Package
Top View
PCLK0
nPCLK0
PCLK1
nPCLK1
V
BB
CLK_SEL
nc
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
nc
V
EE
V
EE
V
CC
V
EE
Q
nQ
V
EE
ICS85301
16-Lead TSSOP
4.4mm x 5.0mm x 0.92mm
package body
G Package
Top View
85301AK
www.icst.com/products/hiperclocks.html
1
REV. A JANUARY 16, 2006