Integrated
Circuit
Systems, Inc.
ICS85301
2:1
D
IFFERENTIAL
-
TO
-LVPECL M
ULTIPLEXER
A
PPLICATION
I
NFORMATION
W
IRING THE
D
IFFERENTIAL
I
NPUT TO
A
CCEPT
S
INGLE
E
NDED
LVCMOS L
EVELS
Figure 1A
shows an example of the differential input that
can be wired to accept single ended LVCMOS levels. The
reference voltage level V
BB
generated from the device is
connected to the negative input. The C1 capacitor should
be located as close as possible to the input pin.
VCC
R1
1K
Single Ended Clock Input
PCLK
V_REF
nPCLK
C1
0.1u
R2
1K
F
IGURE
1A. S
INGLE
E
NDED
LVCMOS S
IGNAL
D
RIVING
D
IFFERENTIAL
I
NPUT
W
IRING THE
D
IFFERENTIAL
I
NPUT TO
A
CCEPT
S
INGLE
E
NDED
LVPECL L
EVELS
Figure 1B
shows an example of the differential input that
can be wired to accept single ended LVPECL levels. The
reference voltage level V
BB
generated from the device is
connected to the negative input.
VCC(or VDD)
CLK_IN
PCLK
VBB
nPCLK
F
IGURE
1B. S
INGLE
E
NDED
LVPECL S
IGNAL
D
RIVING
D
IFFERENTIAL
I
NPUT
www.icst.com/products/hiperclocks.html
8
85301AK
REV. A JANUARY 16, 2006
ICS [ INTEGRATED CIRCUIT SYSTEMS ]
