Integrated
Circuit
Systems, Inc.
ICS83026I-01
L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL F
ANOUT
B
UFFER
Test Conditions
IJ 350MHz
Minimum
1. 5
Typical
2.0
Maximum
350
2.6
15
750
0.03
20% to 80%
IJ 66MHz
67MHz
≤
IJ 166MHz
150
48
46
800
52
54
Units
MHz
ns
ps
ps
ps
ps
%
%
%
T
ABLE
4B. AC C
HARACTERISTICS
,
V
DD
= 3.3V ± 5%, V
DDO
= 2.5V ± 5%, T
A
= -40°C
TO
85°C
Symbol Parameter
f
MAX
t
PD
t
sk(o)
t
sk(pp)
t
jit
t
R
/ t
F
odc
Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
Par t-to-Par t Skew; NOTE 3, 4
Buffer Additive Phase Jitter,
RMS, refer to Additive Phase
Jitter Section
Output Rise/Fall Time
Output Duty Cycle
167MHz
≤
IJ 350MHz
40
60
NOTE 1: Measured from the differential input crossing point to V
DDO
/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V
DDO
/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with
equal load conditions. Using the same type of inputs on each device, the outputs are measured at V
DDO
/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
T
ABLE
4C. AC C
HARACTERISTICS
,
V
DD
= 3.3V ± 5%, V
DDO
= 1.8V ± 5%, T
A
= -40°C
TO
85°C
Symbol Parameter
f
MAX
t
PD
t
sk(o)
t
sk(pp)
t
jit
t
R
/ t
F
odc
Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
Par t-to-Par t Skew; NOTE 3, 4
Buffer Additive Phase Jitter,
RMS, refer to Additive Phase
Jitter Section
Output Rise/Fall Time
Output Duty Cycle
IJ 350MHz
1.9
2.5
Test Conditions
Minimum
Typical
Maximum
350
3.1
15
600
0.03
20% to 80%
IJ 66MHz
67MHz
≤
IJ 166MHz
200
48
43
900
52
57
Units
MHz
ns
ps
ps
ps
ps
%
%
%
167MHz
≤
IJ 350MHz
40
60
NOTE 1: Measured from the differential input crossing point to V
DDO
/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V
DDO
/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with
equal load conditions. Using the same type of inputs on each device, the outputs are measured at V
DDO
/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
83026BMI-01
www.icst.com/products/hiperclocks.html
5
REV. A JANUARY 16, 2006
ICS [ INTEGRATED CIRCUIT SYSTEMS ]
