Integrated
Circuit
Systems, Inc.
ICS83026I-01
L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL F
ANOUT
B
UFFER
Test Conditions
nCLK
CLK
nCLK
CLK
V
IN
= V
DD
= 3.465V
V
IN
= V
DD
= 3.465V
V
IN
= 0V, V
DD
= 3.465V
V
IN
= 0V, V
DD
= 3.465V
-150
-5
0.15
1. 3
V
DD
- 0.85
Minimum
Typical
Maximum
150
150
Units
µA
µA
µA
µA
V
V
T
ABLE
3D. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
DD
= 3.3V ± 5%, V
DDO
= 1.71V
TO
3.465V, T
A
= -40°C
TO
85°C
Symbol
I
IH
I
IL
V
PP
Parameter
Input High Current
Input Low Current
Peak-to-Peak Input Voltage; NOTE 1
V
CMR
Common Mode Input Voltage; NOTE 2, 3
GND + 0.5
NOTE 1: V
PP
can exceed 1.3V provided that there is sufficient offset level to keep V
IL
> 0V.
NOTE 2: For single ended applications
,
the maximum input voltage for CLK, nCLK is V
DD
+ 0.3V.
NOTE 3: Common mode voltage is defined as V
IH
.
T
ABLE
4A. AC C
HARACTERISTICS
,
V
DD
= 3.3V ± 5%, V
DDO
= 3.3V ± 5%, T
A
= -40°C
TO
85°C
Symbol Parameter
f
MAX
t
PD
t
sk(o)
t
sk(pp)
t
jit
t
R
/ t
F
odc
Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
Par t-to-Par t Skew; NOTE 3, 4
Buffer Additive Phase Jitter, RMS, refer to
Additive Phase Jitter Section
Output Rise/Fall Time
Output Duty Cycle
IJ 350MHz
1.3
1. 9
Test Conditions
Minimum
Typical
Maximum
350
2.5
15
900
0.03
20% to 80%
IJ 66MHz
67MHz
≤
IJ 166MHz
15 0
48
45
800
52
55
Units
MHz
ns
ps
ps
ps
ps
%
%
%
167MHz
≤
IJ 350MHz
40
60
NOTE 1: Measured from the differential input crossing point to V
DDO
/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V
DDO
/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with
equal load conditions. Using the same type of inputs on each device, the outputs are measured at V
DDO
/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 6.
83026BMI-01
www.icst.com/products/hiperclocks.html
4
REV. A JANUARY 16, 2006
ICS [ INTEGRATED CIRCUIT SYSTEMS ]
