PRELIMINARY INFORMATION
ICS1726-11
Low EMI Clock Generator
3) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers. Other signal traces should be routed
away from the ICS1726-11. This includes signal traces
just underneath the device, or on layers adjacent to the
ground plane layer used by the device.
External Components
The ICS1726-11 requires a minimum number of
external components for proper operation.
Decoupling Capacitor
A decoupling capacitor of 0.01µF must be connected
between VDD and GND on pins 7 and 2, as close to
these pins as possible. For optimum device
performance, the decoupling capacitor should be
mounted on the component side of the PCB. Avoid the
use of vias in the decoupling circuit.
Crystal Information
The crystal used should be a fundamental mode (do
not use third overtone), parallel resonant. Crystal
capacitors should be connected from pins X1 to ground
and X2 to ground to optimize the initial accuracy. The
value of these capacitors is given by the following
equation:
Series Termination Resistor
When the PCB trace between the clock output and the
load is over 1 inch, series termination should be used.
To series terminate a 50Ω trace (a commonly used
trace impedance) place a 33Ω resistor in series with
the clock line, as close to the clock output pin as
possible. The nominal impedance of the clock output is
20Ω.
Crystal caps (pF) = (C - 6) x 2
L
In the equation, C is the crystal load capacitance. So,
L
for a crystal with a 16 pF load capacitance, two 20 pF
[(16-6) x 2] capacitors should be used.
Spread Spectrum Profile
Tri-level Select Pin Operation
The S1, S0 select pins are tri-level, meaning they have
three separate states to make the selections shown in
the table on page 2. To select the M (mid) level, the
connection to these pins must be eliminated by either
floating them, or tri-stating the driver connected to the
select pin.
The ICS1726-11 low EMI clock generator uses an
optimized frequency slew rate to facilitate down stream
tracking by zero delay buffers and other PLL devices.
The frequency modulation amplitude is constant
despite variations of the input frequency.
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
Modulation Rate
1) The 0.01µF decoupling capacitor should be mounted
on the component side of the board as close to the
VDD pin as possible. No vias should be used between
the decoupling capacitor and VDD pin. The PCB trace
to VDD pin should be kept as short as possible, as
should the PCB trace to the ground via.
Time
2) To minimize EMI, the 33Ω series termination resistor
(if needed) should be placed close to the clock output.
MDS 1726-11 A
3
Revision 092905
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
