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TW8 参数 Datasheet PDF下载

TW8图片预览
型号: TW8
PDF下载: 下载PDF文件 查看货源
内容描述: 16位SIN / COS插补算法的自动校准 [16-BIT SIN/COS INTERPOLATOR WITH AUTO-CALIBRATION]
分类和应用:
文件页数/大小: 63 页 / 1930 K
品牌: ICHAUS [ IC-HAUS GMBH ]
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nar y
iC-TW8
16-BIT SIN/COS INTERPOLATOR
limi
pre
WITH AUTO-CALIBRATION
Rev A2, Page 8/12
ELECTRICAL CHARACTERISTICS
Operating conditions: AVDD = DVDD = 3.1...5.5 V, Tj = -40...+125 °C, reference point AVSS unless otherwise stated
Item
No.
001
002
Symbol
Parameter
Conditions
Min.
AVDD,
DVDD
IDD
Permissable Supply Voltage
AVDD, DVDD
Total Supply Current in AVDD
and DVDD
fin = 1 kHz, Increments 4096, Post-AB Divider
1, error-free boot-up from EEPROM;
VDD = 5 V, 32 MHz crystal
VDD = 3.3 V, 20 MHz crystal
1.4
3.1
Typ.
Max.
5.5
V
Unit
Total Device
25
12
AVDD -
1.0
±12
±50
mA
mA
V
mV
nA
%
Signal Inputs and Amplifiers: SIN+, SIN-, COS+, COS-
101
102
103
105
Vin()
Vos()
Iin()
OFFcorr
Permissible Input Voltage
Amplifier Input Offset Voltage
Input Leakage Current
Correctable Input Offset Voltage
as percentage of input signal amplitude; input
offset voltage is the sum of sensor offset plus
amplifier offset (item 102);
±100
106
Acorr
Correctable SIN/COS Amplitude max(Asin, Acos) / min(Asin, Acos), whereas
Mismatch
Asin and Acos are the SIN/COS input ampli-
tudes respectively.
Correctable SIN/COS Phase
Error
Pull-Up Resistor at SIN+, COS+
(step size 0.052 degree)
MAIN_CFG.pull = 1
1.24
107
108
109
201
202
203
301
302
303
PHIcorr
Rpu()
Rpd()
Vin()
Vos()
Iin()
INL
DNL
N
±53
2
2
0
AVDD
±12
±50
deg
MΩ
MΩ
V
mV
nA
deg
deg
deg
MHz
MHz
MHz
MHz
Pull-Down Resistor at SIN-, COS- MAIN_CFG.pull = 1
Permissible Input Voltage
Input Referred Offset Voltage
Input Leakage Current
Integral Nonlinearity
Differential Nonlinearity
Output Angle Noise
refer to Figure 2, 1 Vpp-diff SIN/COS input with
compensated offset, gain and phase
refer to Figure 2, 1 Vpp-diff SIN/COS input with
compensated offset, gain and phase
1 Vpp-diff SIN/COS input, fin = 0 Hz
AVDD, DVDD = 5 V
AVDD, DVDD = 3.3 V
Tj = 27 °C, MAIN_CLOCK.freq = 0;
AVDD, DVDD = 3.3 V
AVDD, DVDD = 5 V
increasing voltage at DVDD;
xRST tied to DVDD
xRST connected through 68 kΩ to DVSS
0.8
V() = 0 ... DVDD - 1 V
AVDD, DVDD = 5 V, fxtl = 24 MHz by crystal;
pin configuration (EEPROM connected)
ready for serial config. (EEPROM connected)
ready for serial config. (no EEPROM)
6
6
Index Signal Inputs and Amplifier: ZERO+, ZERO-
Converter Performance
0.08
0.02
0.08
32
24
16
20
Clock: XIN, XOUT
401 fxtl
Permissible External Frequency
driven into XOUT
402 fosc
Internal Oscillator Frequency
Reset and Start-Up: xRST
601 DVDDon
DVDD Reset Threshold
2.7
4.0
2.2
40
100
100
tbd.
V
V
V
V
kΩ
ms
ms
ms
602
603
604
605
Vt()hi
Vt()lo
Rpu()
tstart
Input Logic Threshold High
Input Logic Threshold Low
Pull-Up Resistor
Startup Time