iC-TW8 16-BIT SIN/COS INTERPOLATOR
WITH AUTO-CALIBRATION
Rev A2, Page 8/12
ELECTRICAL CHARACTERISTICS
Operating conditions: AVDD = DVDD = 3.1...5.5 V, Tj = -40...+125 °C, reference point AVSS unless otherwise stated
Item Symbol
No.
Parameter
Conditions
Unit
Min.
Typ.
Max.
Total Device
001 AVDD,
DVDD
Permissable Supply Voltage
AVDD, DVDD
3.1
5.5
V
002
IDD
Total Supply Current in AVDD
and DVDD
fin = 1 kHz, Increments 4096, Post-AB Divider
1, error-free boot-up from EEPROM;
VDD = 5 V, 32 MHz crystal
25
12
mA
mA
VDD = 3.3 V, 20 MHz crystal
Signal Inputs and Amplifiers: SIN+, SIN-, COS+, COS-
101 Vin()
Permissible Input Voltage
1.4
AVDD -
1.0
V
102 Vos()
103 Iin()
Amplifier Input Offset Voltage
Input Leakage Current
±12
±50
mV
nA
%
105
OFFcorr
Correctable Input Offset Voltage
as percentage of input signal amplitude; input
offset voltage is the sum of sensor offset plus
amplifier offset (item 102);
±100
1.24
106 Acorr
Correctable SIN/COS Amplitude max(Asin, Acos) / min(Asin, Acos), whereas
Mismatch
Asin and Acos are the SIN/COS input ampli-
tudes respectively.
107 PHIcorr
Correctable SIN/COS Phase
Error
(step size 0.052 degree)
±53
2
deg
MΩ
MΩ
108
Rpu()
Pull-Up Resistor at SIN+, COS+
MAIN_CFG.pull = 1
109 Rpd()
Pull-Down Resistor at SIN-, COS- MAIN_CFG.pull = 1
2
Index Signal Inputs and Amplifier: ZERO+, ZERO-
201 Vin()
202 Vos()
203 Iin()
Permissible Input Voltage
Input Referred Offset Voltage
Input Leakage Current
0
AVDD
±12
V
mV
nA
±50
Converter Performance
301 INL
Integral Nonlinearity
refer to Figure 2, 1 Vpp-diff SIN/COS input with
compensated offset, gain and phase
0.08
0.02
0.08
deg
deg
deg
302 DNL
Differential Nonlinearity
Output Angle Noise
refer to Figure 2, 1 Vpp-diff SIN/COS input with
compensated offset, gain and phase
303
N
1 Vpp-diff SIN/COS input, fin = 0 Hz
Clock: XIN, XOUT
401
402
fxtl
Permissible External Frequency
driven into XOUT
AVDD, DVDD = 5 V
AVDD, DVDD = 3.3 V
6
6
32
24
MHz
MHz
fosc
Internal Oscillator Frequency
Tj = 27 °C, MAIN_CLOCK.freq = 0;
AVDD, DVDD = 3.3 V
AVDD, DVDD = 5 V
16
20
MHz
MHz
Reset and Start-Up: xRST
601
DVDDon
DVDD Reset Threshold
increasing voltage at DVDD;
xRST tied to DVDD
2.7
4.0
V
V
xRST connected through 68 kΩ to DVSS
602 Vt()hi
603 Vt()lo
604 Rpu()
Input Logic Threshold High
Input Logic Threshold Low
Pull-Up Resistor
2.2
V
V
0.8
V() = 0 ... DVDD - 1 V
40
kΩ
605
tstart
Startup Time
AVDD, DVDD = 5 V, fxtl = 24 MHz by crystal;
pin configuration (EEPROM connected)
ready for serial config. (EEPROM connected)
ready for serial config. (no EEPROM)
100
100
tbd.
ms
ms
ms
ICHAUS [ IC-HAUS GMBH ]
