iC-TW8 16-BIT SIN/COS INTERPOLATOR
WITH AUTO-CALIBRATION
Rev A2, Page 5/12
PIN FUNCTIONS
No. Name
I/O
Function
Description
11 SPI_SCLK
Digital in,
with hysteresis
SPI Slave Clock Input
Pin connects to SPI master clock output. The input implements hys-
teresis to avoid double triggering.
This pin must be tied to DVSS if the SPI is not used.
12 nc
These pins have no connection to die. Connect to DVSS on PCB.
13 nc
14 SPI_xSS
Digital in,
low active
SPI Slave Select Input
In 4-pin SPI mode this pin directly connects to the SPI master slave
select output. In case the SPI is operated in 3-pin mode, SPI_xSS
must be tied low to DVSS.
15 DVSS
16 OUTZ
17 OUTB
Ground
Digital Ground
Z Output
Pin must tie to high quality ground, usually a solid PCB plane.
Quadrature interface reference output.
Digital out
Digital out
B Output
In quadrature mode this is output B.
PWM- Output
Z Window
In PWM mode this is PWM-, the inverted output of OUTA.
In Z calibration mode (bit RB_TEST1.z_test = 1) this is the Z window
seen just after the input comparator.
18 OUTA
Digital out
A Output
In quadrature mode this is output A.
PWM+ Output
Z Window
In PWM mode this is PWM+.
In Z calibration mode (bit RB_TEST1.z_test = 1) this is the Z window
used to gate the Z output.
19 STATUS
20 FAULT
Digital out
Digital out
PWM Status Output
Error Status Output
This pin provides proportional status information. Pin can drive a
10 mA LED and is widely configurable. Refer to section Monitoring
Interpolation Quality for details.
Pin is low on error and is capable of driving a 10 mA LED. The error
response can be configured as detailed in section Fault Handling for
details.
21 DVDD
Supply
Digital Power Supply
Configuration Mode
+3.1 V to +5.5 V supply voltage terminal.
DVDD and AVDD must be the same voltage level (5 V or 3.3 V).
22 PINSEL
Digital in,
150 kΩ pull-down Selection
Tie pin to DVSS to enable serial configuration mode.
Tie pin to DVDD to select pin configuration mode.
23 nc
These pins have no connection to die. Connect to DVSS on PCB.
Connect this pin to DVSS on PCB.
24 nc
25 nc
26 reserved
27 SCL
Digital in/out,
10 kΩ pull-up
EEPROM Clock Line
EEPROM Data Line
This pin connects to the EEPROM SCL pin. No external I2C pull-up
resistor is required as 10 kΩ is integrated.
28 SDA
29 WP
Digital in/out,
10 kΩ pull-up
This pin connects to the EEPROM SDA pin. No external I2C pull-up
resistor is required as 10 kΩ is integrated.
Digital out
EEPROM Write Protection This pin acts as the write protect signal and connects to the EEPROM
WP pin. No external pull-up is required as this pin is a push-pull output
actively driving low and high.
30 C0
31 C1
32 C2
33 C3
34 XOUT
If the pin configuration mode is used (pin PINSEL tied high), each pin
functions as 12-level configuration input.
If serial configuration mode is used (pin PINSEL tied low), connect
these pins to DVSS on PCB.
Configuration
Inputs
Analog in
Analog in/out
Analog in
Crystal Terminal
Pin can be left floating if no crystal is used.
An external oscillator or other square wave clock source can be used
to drive this pin. Refer to Providing a Clock.
35 XIN
36 nc
Crystal Terminal
Pin must be tied to AVSS if no crystal is used.
These pins have no connection to die. Connect to DVSS on PCB.
37 nc
38 AVDD
Supply
Analog Power Supply
+3.1 V to +5.5 V supply voltage terminal. Keep it clean!
DVDD and AVDD must be the same voltage level (5 V or 3.3 V).
39 SIN+
40 SIN-
41 COS+
42 COS-
43 nc
Analog in
Analog in
Analog in
Analog in
Sine Input +
Sine Input -
Differential sine signal input. For single ended sensors SIN- must be
biased to an appropriate DC level.
Cosine Input +
Cosine Input -
Differential cosine signal input. For single ended sensors COS- must
be biased to an appropriate DC level.
Pin has no connection to die. Connect to DVSS on PCB.
44 VC
Analog out
Bias Output
Decouple with 1 µF capacitor to AVSS. Do not inject noise into this pins
as it directly impacts ADC conversion noise.
ICHAUS [ IC-HAUS GMBH ]
