iC-TW8 16-BIT SIN/COS INTERPOLATOR
Serial Configuration Mode
Jan 9, 2013 Page SC31/36
cycles. The clamped configuration is useful for sin-
gle-turn absolute applications where there is only
one Sin/Cos input cycle per revolution.
Using PWM Output Mode
As an alternative to the standard AB quadrature out-
put, the iC-TW8 can provide a pulse-width modu-
lated (PWM) output proportional to sensor angle.
This is useful as a direct digital interface between
the interpolator and a subsequent microcontroller or
FPGA in imbedded control applications. Enter
PWM for the Output Mode in the General Configu-
ration tab of the design tool. The A and B outputs
(pins 18 and 17 respectively) become the differen-
tial PWM output; the Z output (pin 16) remains un-
changed.
An external first or second order low-pass filter can
be used to convert the PWM output to a voltage,
which in turn can be sampled by an ADC. Since the
PWM output is generated by a first order delta-
sigma modulator (DSM), a second order filter is
recommended. However, a first order analog RC
filter may be sufficient in simple applications.
R
OUTA
ADC
OUTA
OUTB
OUTZ
PWM+
PWM–
OUTZ
C
OUTB
OUTZ
Microcontroller
with built-in ADC
iC-TW8
iC-TW8
Figure 33: Analog Low-Pass PWM Filter
Figure 31: PWM Output Mode
Alternatively, the PWM output can be directly sam-
pled and digitally filtered by a microcontroller.
FPGA, or PLD. In this case, enable the CLOCK and
FRAME outputs in the General Configuration tab of
the design tool. The CLOCK output (pin 6) can then
be used to synchronously sample the PWM output.
Selecting PWM output mode in the design tool re-
veals the PWM configuration selections. Enter the
desired frequency for the PWM output; the design
tool shows the closest actual frequency available
using the selected crystal. Finally, select whether the
PWM output is clamped or not.
1 Input Cycle
GP Input
GP Input
OUTA
CLOCK
OUTZ
SIN
COS
Microcontroller,
FPGA, or PLD
iC-TW8
0°
90° 180° 270° 360°
100%
Figure 34: Digitally Sampling the PWM Output
PWM Output
(Not Clamped)
This allows an all-digital decimation filter to be im-
plemented. Since a first order DSM is used to gen-
erate the PWM output, a second order restructuring
filter is required for best signal-to-noise perfor-
mance. As with the analog filter, however, a first
order filter may be sufficient for many applications.
0%
100%
PWM Output
(Clamped)
0%
Figure 32: PWM Output Clamp
The typical configuration is not clamped, in which
case the PWM output duty cycle represents the an-
gle of the sensor Sin/Cos inputs over multiple input
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