iC-NQ
13-bit Sin/D CONVERTER WITH CALIBRATION
Rev D1, Page 9/25
OPERATING REQUIREMENTS: BiSS and SSI Interface
Operating Conditions: VDD = 5 V ±10 %, Ta = -25 ... 85 °C; input levels lo = 0 ... 0.45 V, hi = 2.4 V ... VDD
Item
No.
Symbol
Parameter
Conditions
Fig.
Min.
Permissible Clock Period
Clock Signal Hi Level Duration
Clock Signal Lo Level Duration
Permissible Clock Period
Clock Signal Hi Level Duration
Clock Signal Lo Level Duration
Permissible Clock Period
Permissible Clock Halt (idle)
Clock Signal Hi Level Duration
Clock Signal Hi Level Duration
Clock Signal Lo Level Duration
"Logic 0" Hi Level Duration
"Logic 1" Hi Level Duration
read out of register data
CFGTOR selected in accordance with
table on page 15
CFGTOR selected in accordance with
table on page 15
CFGTOS = 0x01
4
4
4
5
5
5
6
6
6
6
6
6
6
10
70
30
250
25
25
100
25
25
4
0
indefinite
t
tor
70
t
tor
30
90
ns
%
TMAR
ns
%
TMAR
%
TMAR
t
tos
Max.
2x t
tos
t
tos
t
tos
ns
ns
ns
ns
ns
ns
µs
Unit
SSI Output (SELSSI = 1)
I001 T
MAS
I002 t
MASh
I003 t
MASl
I004 T
MAS
I005 t
MASh
I006 t
MASl
I007 T
MAR
I008 t
idle
I009 t
MARh
I010 t
MARh
I011 t
MARl
I012 t
MA0h
I013 t
MA1h
BiSS Sensor Mode
BiSS Register Mode
Figure 4: Timing diagram of SSI output.
Figure 5: Timing diagram of BiSS sensor mode.
Figure 6: Timing diagram of BiSS register mode.
ICHAUS [ IC-HAUS GMBH ]
