iC-NQ
13-bit Sin/D CONVERTER WITH CALIBRATION
Rev D1, Page 7/25
ELECTRICAL CHARACTERISTICS
Operating Conditions: VDDA = VDD = 5 V ±10 %, Tj = -40 ... 125 °C, unless otherwise stated
Item Symbol
No.
Parameter
Conditions
Unit
Min.
Typ.
Max.
Zero Comparator
B01 Vos()
Input Offset Voltage
Input Current
V() = Vcm()
-20
-50
1.4
20
50
mV
nA
V
B02 Iin()
V() = 0 V ... VDDA
B03 Vcm()
Common-Mode Input Voltage
Range
VDDA-
1.5
B04 Vdm()
Differential Input Voltage Range
0
VDDA
V
Incremental Outputs A, B, Z and BiSS Interface Output SLO
D01 Vs()hi
D02 Vs()lo
D03 tr()
Saturation Voltage hi
Saturation Voltage lo
Rise Time
Vs()hi = VDD - V(); I() = -4 mA
I() = 4 mA
0.4
0.4
60
V
V
CL() = 50 pF
ns
ns
MΩ
D04 tf()
Fall Time
CL() = 50 pF
60
D05 RL()
Permissible Load at A, B
TMA = 1 (calibration mode)
1
BiSS Interface: Inputs MA, SLI
E01 Vt()hi
Threshold Voltage hi
2
V
V
E02 Vt()lo
Threshold Voltage lo
Hysteresis
0.8
300
-240
20
E03 Vt()hys
E04 Ipu(MA)
E05 Ipd(SLI)
Vt()hys = Vt()hi - Vt()lo
V() = 0 ... VDD - 1 V
V() = 1 ... VDD
mV
µA
µA
Pull-up Current in MA
Pull-down Current in SLI
-120
120
-25
300
E06
fclk(MA)
Permissible Clock Frequency at
MA
SSI protocol
BiSS B protocol: sensor mode
BiSS B protocol: register mode
4
10
0.25
MHz
MHz
MHz
E07 tp(MA-
SLO)
Propagation Delay: MA edge vs. all modes, RL(SLO) ≥ 1 kΩ
10
0
50
ns
SLO output
E08 tbusy()s
E09 tbusy()r
E10 tidle()
Processing Time Sensor Mode
Processing Time Register Mode delay of start bit with read access to EEPROM
Interface Blocking Time powering up with no EEPROM
delay of start bit
0
1
0
2
ms
ms
1.5
EEPROM Interface, Control Logic: Inputs SDA, NERR
F01 Vt()hi
F02 Vt()lo
F03 Vt()hys
Threshold Voltage hi
Threshold Voltage lo
Hysteresis
2
7
V
V
0.8
Vt()hys = Vt()hi - Vt()lo
300
mV
ms
F04 tbusy()cfg Duration of Startup Configuration error free EEPROM access
5
EEPROM Interface, Control Logic: Outputs SDA, SCL, NERR
G01 f()
Write/Read Clock at SCL
Saturation Voltage lo
Pull-up Current
20
100
0.45
-75
60
kHz
V
G02 Vs()lo
G03 Ipu()
G04 ft()
I() = 4 mA
V() = 0 ... VDD - 1 V
CL() = 50 pF
-600
10
-300
µA
ns
Fall Time
G05 tmin()lo
Error Signal Indication Time at
NERR (lo signal)
MA = hi, no BiSS access, amplitude or frequeny
error
ms
G06 Tpwm()
G07 RL()
Error Signal PWM Cycle Duration fosc() subdivided 222
at NERR
60.7
ms
Permissible Load at SDA, SCL
TMA = 1 (calibration mode)
1
MΩ
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