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IC-NQTSSOP20ET-40/125 参数 Datasheet PDF下载

IC-NQTSSOP20ET-40/125图片预览
型号: IC-NQTSSOP20ET-40/125
PDF下载: 下载PDF文件 查看货源
内容描述: 校准13位仙/ D转换器 [13-bit Sin/D CONVERTER WITH CALIBRATION]
分类和应用: 转换器
文件页数/大小: 25 页 / 1070 K
品牌: ICHAUS [ IC-HAUS GMBH ]
 浏览型号IC-NQTSSOP20ET-40/125的Datasheet PDF文件第6页浏览型号IC-NQTSSOP20ET-40/125的Datasheet PDF文件第7页浏览型号IC-NQTSSOP20ET-40/125的Datasheet PDF文件第8页浏览型号IC-NQTSSOP20ET-40/125的Datasheet PDF文件第9页浏览型号IC-NQTSSOP20ET-40/125的Datasheet PDF文件第11页浏览型号IC-NQTSSOP20ET-40/125的Datasheet PDF文件第12页浏览型号IC-NQTSSOP20ET-40/125的Datasheet PDF文件第13页浏览型号IC-NQTSSOP20ET-40/125的Datasheet PDF文件第14页  
iC-NQ  
13-bit Sin/D CONVERTER WITH CALIBRATION  
Rev D1, Page 10/25  
PARAMETER and REGISTER  
Signal Monitoring  
and Error Messages . . . . . . . . . . . . . . . . . . . . . . . Page 17  
SELAMPL: Amplitude Monitoring, function  
Register Description . . . . . . . . . . . . . . . . . . . . . . .Page 10  
Signal Conditioning . . . . . . . . . . . . . . . . . . . . . . . Page 11  
GAIN:  
SINOFFS:  
Gain Select  
Offset Calibration Sine  
AMPL:  
AERR:  
FERR:  
Amplitude Monitoring, thresholds  
Amplitude Error  
Frequency Error  
COSOFFS: Offset Calibration Cosine  
REFOFFS: Offset Calibration Reference  
RATIO:  
PHASE:  
Amplitude Calibration  
Phase Calibration  
Test Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 18  
TMODE:  
TMA:  
Test Mode  
Analog Test Mode  
Converter Function . . . . . . . . . . . . . . . . . . . . . . . . Page 12  
SELRES:  
HYS:  
Resolution  
Hysteresis  
Max. Permissible Converter Frequency  
BiSS Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 19  
FCTR:  
CFGTOS:  
CFGTOR:  
M2S:  
Interface Timeout  
Interface Timeout  
Period Counter Output  
Incremental Signals . . . . . . . . . . . . . . . . . . . . . . . Page 15  
CFGABZ:  
ROT:  
Output A, B, Z  
Direction of Rotation  
Period Counter Configuration  
BiSSMOD: Protocol Version  
CBZ:  
ENRESDEL: Output Turn-On Delay  
SELSSI:  
CFGSSI:  
RPL:  
SSI Compatibility  
SSI Output  
Register Access Safety Level  
ZPOS:  
CFGZ:  
CFGAB:  
Zero Signal Position  
Zero Signal Length  
Zero Signal Logic  
OVERVIEW  
Adr  
0x00  
0x01  
0x02  
0x03  
0x04  
0x05  
0x06  
0x07*  
0x08  
0x09  
0x0A  
0x0B  
0x0C  
0x0D  
0x0E  
0x0F  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
BiSSMOD  
M2S(1:0)  
SELRES(4:0)  
HYS(2:0)  
SELSSI  
ZPOS(4:0)  
ENRESDEL  
ROT  
CBZ  
CFGABZ(1:0)  
RPL(1:0)  
CFGZ(1:0)  
CFGSSI(1:0)  
CFGAB(1:0)  
AERR  
FERR  
FCTR(7:0)  
FCTR(14:8)  
CFGTOR(1:0)  
CFGTOS(1:0)  
TMODE(2:0)  
TMA  
Reserved address / internal use  
GAIN(3:0)  
RATIO(3:0)  
SINOFFS(7:0)  
COSOFFS(7:0)  
PHASE(5:0)  
REFOFFS  
RATIO(4)  
SELAMPL  
AMPL(1:0)  
CRC(7:0) check sum over address 0-14 with CRC polynomial: "100100111" (read out of EEPROM)  
EEPROM  
0x00 - 0xF  
0x10 -  
0x1F  
Reserved EEPROM register section storing iC-NQ device setup  
Free EEPROM registers  
0x20 -  
0x77  
0x10 - 0x67  
0x68 - 0x6F  
0x78 -  
0x7F  
EEPROM: BiSS Identifier, ROM: Device ID iC-NQ X3: 4E 51 58 33 {ADR0} 00 69 43**  
As no access protections are selected all registers are accessible by read and write operations (see RPL).  
*) Programming to value 0x00 is recommended. **) iC-NQ V2: 4E 51 56 32 {Adr 0x00} 00 69 43  
Table 5: Register layout  
 
 
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