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IC-NQLTSSOP20 参数 Datasheet PDF下载

IC-NQLTSSOP20图片预览
型号: IC-NQLTSSOP20
PDF下载: 下载PDF文件 查看货源
内容描述: 带SSI接口13位仙/ D转换器 [13-bit Sin/D CONVERTER WITH SSI INTERFACE]
分类和应用: 转换器
文件页数/大小: 24 页 / 898 K
品牌: ICHAUS [ IC-HAUS GMBH ]
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iC-NQL  
13-bit Sin/D CONVERTER WITH SSI INTERFACE  
Rev B1, Page 23/24  
DESIGN REVIEW: Notes On Chip Functions  
iC-NQL X2  
iC-NQL X3  
No.  
1
Function, Parameter/Code  
Description and Application Hints  
ZPOS  
Illegal settings:  
0x01...0x07, 0x09...0x0F,  
0x11...0x17, 0x19...0x1F  
Illegal settings of ZPOS delay accurate converter operation following power on.  
Depending on the sin/cos input signals (phase angle) the A/B outputs can  
provide pulses causing an external counter to alternately count up and down.  
This may disturb the startup of a drive if the motion controller tolerates only single  
A/B edges during standstill checking.  
The converter operation is again accurate when the sin/cos input signals have  
changed, by a maximum of 45 angular degrees.  
2
3
M2S  
Illegal settings:  
0x02, 0x03  
Illegal settings, enabling a period counter output of 12 or 24 bits, may cause  
position data jumping with fast changes in the direction of count (e.g. applications  
with length gauges).  
It is thus advisable to use 8-bit period counting (M2S 0x01) and to capture the  
overflow in the external microcontroller.  
Pin DATA  
When cycling power pin DATA may show high or low level initially.  
With pin TEST = low (e.g. pin open) at least a single low pulse at pin CLK is  
required to trigger pin DATA to show a high level after the timeout has elapsed.  
When continuing the clock signal after completion of data output, additional zero  
bits are output.  
With pin TEST = high (e.g. pin wired to VDD) only the timeout needs to elapse to  
trigger pin DATA showing high level. When continuing the clock signal after  
completion of data output, additional one bits are output.  
Table 36: Notes on chip functions  
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