iC-NQL
13-bit Sin/D CONVERTER WITH SSI INTERFACE
Rev B1, Page 19/24
SSI INTERFACE
Signal Names
After each communication cycle the SSI interface re-
Name
P
Description
turns to its idle state when the monoflop timeout ttos
has elapsed. This temporal condition also determines
up to which clock line pause duration the iC-NQL re-
tains the current data output cycle - the master may
thus not undershoot a minimum clock frequency of
f(CLK)min.
Period counter (P7 is MSB)
Sensor data (S0 is LSB)
Error messages
S
E
Stop
Low signal
Table 32: Signal Names
CFGTOS
Adr 0x06, Bit 5:4
Timeout ttos
The angle conversion is halted for one clock cycle as
soon as the interface receives the first rising edge on
CLK, what is the trigger signal to output updated posi-
tion data. The halt duration must be taken into consid-
eration when calculating the maximum input frequency.
Code
Ref. clock
counts
f(CLK) min*
0x00
0x01
0x02
0x03
Note
typ. 128 µs
typ. 16 µs
typ. 4 µs
256-259
32-35
8-11
11 kHz
88 kHz
352 kHz
typ. 1 µs
2-5
1.41 MHz
(see El. Char.
M2S
Code
0x00
0x01
Adr 0x00, Bit 6:5
32
fosc
A ref. clock count is equal to
A01 ).
*The permissible max. clock frequency is specified
by item E05 .
Period Counter Output
-
P(7:0)
Table 33: Period Counter Output
Table 31: Monoflop Time (SSI Timeout)
CFGSSI
Code
0x00
Adr 0x03, Bit 7:6
Additional bits
E1, E0, zero bit
none
Ring register operation
The iC-NQL position data output contains the period
counter (P) with a bit length of 0 or 8 bits (selected by
M2S), the angle value (S) with a bit length of 2 to 13
bits (depending on SELRES), and up to 3 add-on bits
(error messages E1 and E0 plus a zero bit). Gener-
ally, the data output is in binary format starting with the
MSB.
no
0x01
no
0x02
E1, E0, zero bit
none
yes
yes
0x03
Table 34: SSI Output Options
ICHAUS [ IC-HAUS GMBH ]
