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IC-NQL 参数 Datasheet PDF下载

IC-NQL图片预览
型号: IC-NQL
PDF下载: 下载PDF文件 查看货源
内容描述: 带SSI接口13位仙/ D转换器 [13-bit Sin/D CONVERTER WITH SSI INTERFACE]
分类和应用: 转换器
文件页数/大小: 24 页 / 898 K
品牌: ICHAUS [ IC-HAUS GMBH ]
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iC-NQL  
13-bit Sin/D CONVERTER WITH SSI INTERFACE  
Rev B1, Page 7/24  
ELECTRICAL CHARACTERISTICS  
Operating Conditions: VDDA = VDD = 5 V ±10 %, Tj = -40 ... 125 °C, unless otherwise stated  
Item Symbol  
No.  
Parameter  
Conditions  
Unit  
Min.  
Typ.  
Max.  
Zero Comparator  
B01 Vos()  
Input Offset Voltage  
Input Current  
V() = Vcm()  
-20  
-50  
1.4  
20  
50  
mV  
nA  
V
B02 Iin()  
V() = 0 V ... VDDA  
B03 Vcm()  
Common-Mode Input Voltage  
Range  
VDDA-  
1.5  
B04 Vdm()  
Differential Input Voltage Range  
0
VDDA  
V
Incremental Outputs A, B, Z  
SSI Interface Output DATA  
D01 Vs()hi  
D02 Vs()lo  
D03 tr()  
Saturation Voltage hi  
Vs()hi = VDD - V(); I() = -4 mA  
I() = 4 mA  
0.4  
0.4  
60  
V
V
Saturation Voltage lo  
Rise Time  
CL() = 50 pF  
ns  
ns  
MΩ  
D04 tf()  
Fall Time  
CL() = 50 pF  
60  
D05 RL()  
Permissible Load at A, B  
TMA = 1 (calibration mode)  
1
SSI Interface: Input CLK  
E01 Vt()hi  
E02 Vt()lo  
E03 Vt()hys  
E04 Ipu()  
E05 fclk()  
Threshold Voltage hi  
2
V
V
Threshold Voltage lo  
Hysteresis  
0.8  
300  
-240  
Vt()hys = Vt()hi - Vt()lo  
V() = 0 ... VDD - 1 V  
mV  
µA  
Pull-up Current in CLK  
-120  
-25  
4
Permissible Clock Frequency at  
CLK  
MHz  
E06 tp(CLK-  
DATA)  
Propagation Delay: CLK edge vs. all modes, RL(SLO) 1 kΩ  
10  
50  
ns  
DATA output  
E07 tbusy()  
E08 tidle()  
Processing Time  
0
1
Interface Blocking Time  
powering up with no EEPROM  
1.5  
2
ms  
EEPROM Interface, Control Logic: Inputs SDA, NERR  
F01 Vt()hi  
F02 Vt()lo  
F03 Vt()hys  
Threshold Voltage hi  
Threshold Voltage lo  
Hysteresis  
V
V
0.8  
Vt()hys = Vt()hi - Vt()lo  
300  
mV  
ms  
F04 tbusy()cfg Duration of Startup Configuration error free EEPROM access  
5
7
EEPROM Interface, Control Logic: Outputs SDA, SCL, NERR  
G01 f()  
Write/Read Clock at SCL  
Saturation Voltage lo  
Pull-up Current  
20  
100  
0.45  
-75  
60  
kHz  
V
G02 Vs()lo  
G03 Ipu()  
G04 ft()  
I() = 4 mA  
V() = 0 ... VDD - 1 V  
CL() = 50 pF  
-600  
10  
-300  
µA  
ns  
Fall Time  
G05 tmin()lo  
Error Signal Indication Time at  
NERR (lo signal)  
CLK = hi, no amplitude or frequeny error  
ms  
G06 Tpwm()  
G07 RL()  
Error Signal PWM Cycle Duration fosc() subdivided by 222  
at NERR  
60.7  
ms  
Permissible Load at SDA, SCL  
TMA = 1 (calibration mode)  
1
MΩ  
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