iC-NQL
13-bit Sin/D CONVERTER WITH SSI INTERFACE
Rev B1, Page 4/24
PACKAGES TSSOP20 (according to JEDEC Standard)
PIN CONFIGURATION
PIN FUNCTIONS
TSSOP20 4.4 mm, lead pitch 0.65 mm
No. Name Function
1 PCOS Input Cosine +
2 NCOS Input Cosine -
3 VDDA +5 V Supply Voltage (analog)
4 GNDA Ground (analog)
5 VREF Reference Voltage Output
6 A
7 B
8 Z
Incremental Output A
Analog signal COS+ (TMA mode)
PWM signal for Offset Sine (Calib.)
Incremental Output B
Analog signal COS- (TMA mode)
PWM signal for Offset Cosine (Calib.)
Output Index Z
PWM signal for Phase/Ratio (Calib.)
Ground
9 GND
10 VDD
+5 V Supply Voltage (digital)
11 TEST Test Input
12 CLK
13 DATA
14 SDA
SSI interface, clock line
SSI interface, data output
EEPROM interface, data line
Analog signal SIN+ (TMA mode)
EEPROM interface, clock line
Analog signal SIN- (TMA mode)
15 SCL
16 NERR Error Input/Output, active low
17 PZERO Input Zero Signal +
18 NZERO Input Zero Signal -
19 PSIN
20 NSIN
Input Sine +
Input Sine -
External connections linking VDDA to VDD and GND to GNDA are required. The test input may remain unwired
or can be linked to VDD (please note the hints given by chapter Design Review regarding the signal of pin DATA).
ICHAUS [ IC-HAUS GMBH ]
