iC-NQL
13-bit Sin/D CONVERTER WITH SSI INTERFACE
Rev B1, Page 10/24
PARAMETERS and REGISTERS
Register Description . . . . . . . . . . . . . . . . . . . . . . .Page 10 ZPOS:
Zero Signal Position
CFGZ:
CFGAB:
Zero Signal Length
Zero Signal Logic
Signal Conditioning . . . . . . . . . . . . . . . . . . . . . . . Page 11
GAIN:
Gain Select
SINOFFS:
Offset Calibration Sine
Signal Monitoring
COSOFFS: Offset Calibration Cosine
REFOFFS: Offset Calibration Reference
and Error Messages . . . . . . . . . . . . . . . . . . . . . . . Page 17
SELAMPL: Amplitude Monitoring, function
RATIO:
PHASE:
Amplitude Calibration
Phase Calibration
AMPL:
AERR:
FERR:
Amplitude Monitoring, thresholds
Amplitude Error
Frequency Error
Converter Function . . . . . . . . . . . . . . . . . . . . . . . . Page 12
SELRES:
HYS:
FCTR:
Resolution
Hysteresis
Max. Permissible Converter Frequency
Test Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 18
TMODE:
TMA:
Test Mode
Analog Test Mode
Incremental Signals . . . . . . . . . . . . . . . . . . . . . . . Page 15
CFGABZ:
ROT:
SSI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 19
Output A, B, Z
Direction of Rotation
Period Counter Configuration
CFGTOS:
M2S:
CFGSSI:
Interface Timeout
Period Counter Output
SSI Output Options
CBZ:
ENRESDEL: Output Turn-On Delay
OVERVIEW
Adr
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
Note
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
AERR
0
Bit 0
0
M2S(1:0)
SELRES(4:0)
HYS(2:0)
1
ZPOS(4:0)
ENRESDEL
ROT
CBZ
CFGABZ(1:0)
CFGZ(1:0)
CFGSSI(1:0)
CFGAB(1:0)
0
0
FERR
FCTR(7:0)
0
0
0
FCTR(14:8)
0
0
0
CFGTOS(1:0)
TMODE(2:0)
0
TMA
0
0
0
GAIN(3:0)
RATIO(3:0)
SINOFFS(7:0)
COSOFFS(7:0)
PHASE(5:0)
REFOFFS
RATIO(4)
0
0
0
0
0
0
0
0
0
0
0
0
0
SELAMPL
AMPL(1:0)
0
0
0
0
0
0
0
0
CRC(7:0) check sum over address 0x00-0x0E with CRC polynomial: "100100111" (read out of EEPROM)
Registers not in use must be set to zero unless otherwise noted.
Table 5: Register layout
ICHAUS [ IC-HAUS GMBH ]
