iC-NQI
preliminar y
Rev A2, Page 7/26
13-bit Sin/D CONVERTER WITH CALIBRATION
ELECTRICAL CHARACTERISTICS
Operating Conditions: VDDA = VDD = 5 V ±10 %, Tj = -40 ... 125 °C, unless otherwise stated
Item
No.
B01
B02
B03
B04
Symbol
Parameter
Conditions
Min.
Vos()
Iin()
Vcm()
Vdm()
Input Offset Voltage
Input Current
Common-Mode Input Voltage
Range
Differential Input Voltage Range
Saturation Voltage hi
Saturation Voltage lo
Rise Time
Fall Time
Permissible Load at A, B
Threshold Voltage hi
Threshold Voltage lo
Hysteresis
Pull-up Current in CLK
Permissible Clock Frequency at
CLK
Vt()hys = Vt()hi - Vt()lo
V() = 0 ... VDD - 1 V
V() = 1 ... VDD
SSI protocol
BiSS B/C or C unidir. protocols
Register communication (NPRG = lo)
10
0
NPRG = lo; with read access to EEPROM
NPRG = lo; powering up with no EEPROM
1
0
0.8
300
-240
20
-120
120
-25
300
4
10
0.25
50
0
2
1.5
2
0.8
Vt()hys = Vt()hi - Vt()lo
300
5
20
I() = 4 mA
V() = 0 ... VDD - 1 V
CL() = 50 pF
CLK = hi (keine Datenausgabe), amplitude or
frequeny error
10
60.7
1
-600
-300
7
100
0.45
-75
60
ms
ms
V
V
mV
ms
kHz
V
µA
ns
ms
ms
MΩ
Vs()hi = VDD - V(); I() = -4 mA
I() = 4 mA
CL() = 50 pF
CL() = 50 pF
TMA = 1 (calibration mode)
1
2
V() = Vcm()
V() = 0 V ... VDDA
-20
-50
1.4
0
Typ.
Max.
20
50
VDDA-
1.5
VDDA
0.4
0.4
60
60
mV
nA
V
V
V
V
ns
ns
MΩ
V
V
mV
µA
µA
MHz
MHz
MHz
ns
Unit
Zero Comparator
Incremental Outputs A, B, Z and 2W Interface Output DAT
D01 Vs()hi
D02 Vs()lo
D03 tr()
D04 tf()
D05 RL()
E01
E02
E03
E04
E05
E06
Vt()hi
Vt()lo
Vt()hys
Ipu(CLK)
fclk(CLK)
2W Interface: Clock Input CLK, Programming Enable NPRG
Ipd(NPRG) Pull-down Current in NPRG
E07
E08
E09
E10
F01
F02
F03
F04
tp(CLK-
DAT)
tbusy()
tbusy()r
tidle()
Vt()hi
Vt()lo
Vt()hys
tbusy()cfg
Propagation Delay: CLK edge vs. RL(DAT)
≥
1 kΩ (see Fig. 4)
DAT output
Processing Time
Processing Time Register Com-
munication (start bit delay)
Interface Blocking Time
Threshold Voltage hi
Threshold Voltage lo
Hysteresis
Duration of Startup Configuration error free EEPROM access
Write/Read Clock at SCL
Saturation Voltage lo
Pull-up Current
Fall Time
Error Signal Indication Time at
NERR (lo signal)
EEPROM Interface, Control Logic: Inputs SDA, NERR
EEPROM Interface, Control Logic: Outputs SDA, SCL, NERR
G01 f()
G02 Vs()lo
G03 Ipu()
G04 ft()
G05 tmin()lo
G06 Tpwm()
G07 RL()
Error Signal PWM Cycle Duration fosc() subdivided 2
22
at NERR
Permissible Load at SDA, SCL
TMA = 1 (calibration mode)
ICHAUS [ IC-HAUS GMBH ]
