iC-NQI
13-bit Sin/D CONVERTER WITH CALIBRATION
Rev A2, Page 11/26
SIGNAL CONDITIONING
Input stages SIN and COS are configured as instru- programmed to register GAIN according to the follow-
mentation amplifiers. The amplifier gain must be se- ing table. Half of the supply voltage is output to VREF
lected in accordance with the sensor signal level and as center voltage to help DC level adaptation.
GAIN
Adr 0x08, Bit 7:4
Sine/Cosine input signal levels Vin()
Average value (DC)
Amplitude
Single-ended
Code
0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09
0x08
0x07
0x06
0x05
0x04
0x03
0x02
0x01
0x00
Amplification
80.000
66.667
53.333
40.000
33.333
28.571
26.667
20.000
14.287
10.000
8.000
Differential
Differential
Single-ended
up to 50 mVpp
up to 60 mVpp
up to 75 mVpp
up to 0.1 Vpp
up to 0.12 Vpp
up to 0.14 Vpp
up to 0.15 Vpp
up to 0.2 Vpp
up to 0.28 Vpp
up to 0.4 Vpp
up to 0.5 Vpp
up to 0.6 Vpp
up to 0.75 Vpp
up to 1 Vpp
up to 100 mVpp
up to 120 mVpp
up to 0.15 Vpp
up to 0.2 Vpp
up to 0.24 Vpp
up to 0.28 Vpp
up to 0.3 Vpp
up to 0.4 Vpp
up to 0.56 Vpp
up to 0.8 Vpp
up to 1 Vpp
0.7 V ... VDDA - 1.2 V
0.7 V ... VDDA - 1.2 V
0.7 V ... VDDA - 1.2 V
1.2 V ... VDDA - 1.2 V
1.2 V ... VDDA - 1.2 V
0.7 V ... VDDA - 1.2 V
1.2 V ... VDDA - 1.2 V
0.7 V ... VDDA - 1.2 V
1.2 V ... VDDA - 1.3 V
1.2 V ... VDDA - 1.3 V
0.8 V ... VDDA - 1.4 V
0.8 V ... VDDA - 1.4 V
0.9 V ... VDDA - 1.5 V
1.2 V ... VDDA - 1.6 V
1.2 V ... VDDA - 1.7 V
1.3 V ... VDDA - 1.8 V
0.8 V ... VDDA - 1.2 V
0.8 V ... VDDA - 1.2 V
0.8 V ... VDDA - 1.2 V
1.3 V ... VDDA - 1.3 V
1.3 V ... VDDA - 1.3 V
0.8 V ... VDDA - 1.3 V
1.3 V ... VDDA - 1.3 V
0.8 V ... VDDA - 1.3 V
1.4 V ... VDDA - 1.4 V
1.4 V ... VDDA - 1.5 V
1.0 V ... VDDA - 1.6 V
1.1 V ... VDDA - 1.7 V
1.3 V ... VDDA - 1.9 V
1.7 V ... VDDA - 2.1 V
1.8 V ... VDDA - 2.3 V
2.0 V ... VDDA - 2.6 V
6.667
up to 1.2 Vpp
up to 1.5 Vpp
up to 2 Vpp
5.333
4.000
3.333
up to 1.2 Vpp
up to 1.5 Vpp
up to 2.4 Vpp
up to 3 Vpp
2.667
Table 6: Gain select
SINOFFS
Adr 0x09, Bit 7:0
RATIO
Code
0x00
Adr 0x0B, Bit 0, Adr 0x08, Bit 3:0
COSOFFS Adr 0x0A, Bit 7:0
COS / SIN
1.0000
1.0067
...
Code
0x10
0x11
...
COS / SIN
1.0000
0.9933
...
Code
0x00
0x01
...
Output offset
0 V
Input offset
0 V
0x01
-7.8125 mV
...
-7.8125* mV / GAIN
...
...
0x0F
1.1
0x1F
0.9000
0x7F
0x80
0x81
...
-0.9922 V
0 V
-0.9922 V / GAIN
0 V
Table 9: Amplitude Calibration
+7,8125 mV
...
+7.8125 mV / GAIN
...
PHASE
Code
0x00
0x01
...
Adr 0x0B, Bit 7:2
0xFF
Notes
+0.9922 V
+0.9922 V / GAIN
Phase shift
90°
Code
0x20
0x21
...
Phase shift
90°
*) With REFOFFS = 0x00 und VDDA = 5 V.
90.703125°
...
89.296875°
...
Table 7: Offset calibration sine/cosine
0x12
...
102.65625°
102.65625°
102.65625°
0x32
...
77.34375°
77.34375°
77.34375°
REFOFFS Adr 0x0B, Bit 1
Code
0x00
Reference voltage
0x1F
0x3F
Depending on VDDA
(example of application: MR sensors)
Table 10: Phase calibration
0x01
Not depending on VDDA
(example of application: Sin/Cos encoders)
Table 8: Offset calibration reference
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