iC-NQ
13-bit Sin/D CONVERTER WITH CALIBRATION
Rev D1, Page 19/25
BiSS INTERFACE
Serial BiSS communication differentiates between the Protocol and Data Format
fast cyclic transmission of sensor data for the output of
angle position and period counter data and the trans-
mission of register data which can include bidirectional
read and write access.
The required mode of communication is initiated by the
interface master; as a slave iC-NQ determines up to
which maximum clock interval the selected mode is re-
tained. Sensor mode timeout ttos and register mode
timeout ttor thus give the master a minimum clock fre-
quency of fclk(MA)min.
CFGTOS
Adr 0x06, Bit 5:4
Code
Timeout ttos
Sensor mode
Ref. clock
counts
fclk(MA) min*
Figure 18: BiSS B Protocol
0x00
typ. 128 µs
typ. 16 µs
256-259
32-35
8-11
11 kHz
0x01
88 kHz
Single-Cycle Data Channel: SCD
0x02
typ. 4 µs
352 kHz
1.41 MHz
Bits
Type
Label
0x03
typ. 1 µs
2-5
0, 8
DATA
Period Counter P(7:0)
Period Counter P(23:0)*
(multiturn position)
CFGTOR
Code
Adr 0x06, Bit 7:6
0,8, 12, 24*
Timeout ttor
Regist. mode
Ref. clock
counts
fclk(MA) min*
3...13
DATA
Angle Data S(12:0):
3 to 13 bits (singleturn position)
0x00
0x01
0x02
0x03
Notes
typ. 1 ms
2049-2060
513-514
67-68
1.4 kHz
5.5 kHz
42 kHz
–
typ. 256 µs
typ. 32 µs
1
1
5
ERROR
ERROR
CRC
Error bit E1 (amplitude error)
Error bit E0 (frequency error)
not permitted
–
Polynomial 0x25
32
fosc
A ref. clock count is equal to
A01 ). The permissible max. clock frequency is
specified by item E06 .
(see El. Char.
x5 + x2 + x0 (inverted bit output)
6*
CRC
Polynomial 0x43*
x6 + x1 + x0 (inverted bit output)
Multicycle Data Channel: MCD - not in use
Table 31: Interface Timeouts
Bits
1
Type
Label
zero bit
M2S
Adr 0x00, Bit 6:5
Register Data Channel: CD
SCD
MCD
Bits
3
Type
ID
Label
Code
SCD*
CRC Poly.
not in use
Slave ID
Chip releases iC-NQ X2, iC-NQ X3:
7
ADR
WNR
CRC
Register Address
Write-Not-Read Command
0x00
0x01
-
0x25
0x25
1 zero bit
1 zero bit
1
P(7:0)
4
Polynomial 0x13
x4 + x1 + x0 (inverted bit output)
Chip release iC-NQ V2:
0x00
0x01
0x02
0x03
Notes
-
0x25
0x25
0x43
0x43
1 zero bit
1 zero bit
1 zero bit
n/a
Adr
Content
P(7:0)
P(11:0)
P(23:0)
8
4
0x10.. 1F
0x20.. 77
0x78.. 7F
CRC
Device Configuration Data
OEM Daten
BiSS Identifier
*) Period counter output via SCD
Polynomial 0x13
x4 + x1 + x0 (inverted bit Output)
Table 32: Period Counter Output
Table 34: BiSS Data Channels
*) For chip release iC-NQ V2
BiSSMOD Adr 0x00, Bit 7
Code
0x00
0x01
Version
Description
B
C
BiSS B without multicycle data
Transparency for BiSS C
Table 33: Protocol Version
ICHAUS [ IC-HAUS GMBH ]
