iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 27/39
OUTPUT SETTINGS AND ZERO SIGNAL
The set interpolation factor IPF determines the num- Zero Signal Generation
ber of A/B signal cycles generated internally which are The generation of the zero signal is dependant on the
counted via register POS to enable the positioning of internal enable signal ZIn which is produced by com-
the zero pulse. At a sine/cosine phase angle of zero paring the processed X1 and X2 input signals. The
degree the A/B cycle count starts at POS = 0, and the offset calibration of CH0 influences the width of the en-
highest cycle count is reached when POSmax = IPF-1. able signal so that the correct position of ZIn should be
The internal A/B signal cycle adheres to the following checked before the zero signal logic is configured. In
pattern:
Mode ABZ this is possible at the error signal output
(pin ERR; required settings are EMASKA = 0x010 and
EMTD = 0x0).
A 1 1 0 0
B 1 0 0 1
Table 45: Internal A/B Signal Cycle
Inversions and reversals can be selected for the output
of the A/B/Z signals and any logic combination for the
output of the zero signal. The output logic pairs param-
eters CFGABZ in accordance with the table below:
CFGABZ
Adr 0x19, bit 7:0
Figure 7: Signal path from ZIn to PZ/NZ
Bit
7
Function and Description
Output inversion for channel A: PA<>NA
PA = P1i xor CFGABZ(7)
The positioning of the zero signal by CFGZPOS is rel-
ative to the internal A/B cycle count POS. A cycle must
be selected across which enable signal ZIn is centered
as far as is possible. For cycle counts which cannot be
achieved due to a smaller interpolation factor no zero
signal is generated.
6
5
4
Output inversion for channel B: PB<>NB
PB = P2i xor CFGABZ(6)
Output inversion for index channel: PZ<>NZ
PZ = P0i xor CFGABZ(5)
Exchange of A/B signal assignation
0: P1i = A, P2i = B
1: P1i = B, P2i = A
CFGZPOS Adr 0x1A, bit 7:0
Zero Signal Logic CFGABZ(3:0)
Enable for A = 1, B = 1
Enable for A = 1, B = 0
Enable for A = 0, B = 0
Enable for A = 0, B = 1
Bit
7
Description
3
2
1
0
Mask Enable
(zero signal position determined by POS)
(6:0)
POS = A/B cycle count nl (releases zero signal
output)
Table 46: Output Logic
Table 47: Zero Signal Positioning
ENZFF
Adr 0x02, bit 4
Bit
0
Description
Zero signal output with state change of P0i
Zero signal output synchronized with A/B signal
1
Table 48: Zero Signal Synchronization
Figure 6: Signal Path from A and B to PA/NA and
PB/NB
ICHAUS [ IC-HAUS GMBH ]
