iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 17/39
OPERATING MODES
iC-MQ has various modes of operation, for which the coder quadrature signal with a zero pulse. Only in
functions of outputs PA, NA, PB, NB, PZ, NZ and ERR these modes are the line drivers and the reverse po-
are altered.
larity protection feature active.
Two operating modes can be selected for the out- In order to condition the input signals and to cali-
put of the angle position in normal operation. Mode brate and test iC-MQ Calibration and Test modes are
191/193 provides control signals for devices compati- available. Digital and analog test signals are pro-
ble with 74HC191 or 74HC193, whereas in Mode ABZ vided; the latter must always be measured at high load
the angle position is output incrementally as an en- impedance.
MODE(3:0)
Code
0x00
0x0F
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
Addr. 0x02; bit 3:0
Operating Mode
Mode ABZ
Mode 191/193
Calibration 1
Calibration 2
Test 3*
PA
NA
PB
NB
PZ
NZ
ERR
ERR
ERR
IERR
A
not(A)
CPU
B
not(B)
nU/D
IBN
Z
not(Z)
nPL
CPD
CP
MR
TANAZ(2)
PCH1
VPAH
PS_out
PSIN
PCH1I
VTs
VREFIZ
NCH1
VPD
VREFISC
PCH2
—
PCH0
VDC1
IPF
NCH0
VDC2
V05
NCH2
CGUCK
NC_out
NCOS
NCH2I
—
IERR
IERR
IERR
res.
Test 4*
NS_out
NSIN
NCH1I
VTth
PC_out
PCOS
PCH2I
—
PZO
PZO
VDC1
VTTFE
NZO
NZO
VDC2
VTTSE
Test 5*
Test 6*
Calibration 3
Lo-Signal
Hi-Signal
Test 10*
ERR
All outputs and SCL, SDA, ERR to low level
All outputs to high level
TP
A4
A
CLK6
A8
CLK1
B4
CLK3/8
B8
ZIn
ZIn
Z
CLK4
TP1
not(Z)
—
System Test*
Test 12*
ERR
ERR
—
not(A)
—
B
not(B)
—
—
—
—
—
IDDQ Test*
Hints
All PU/PD resistors, oscillator and analog supply voltage deactivated.
*) Test function for iC-Haus device test only.
Table 13: Operating Modes
Mode 191/193
Mode ABZ
Pin
PA
Signal
CPD
CPU
CP
Description
In Mode ABZ A/B signals are generated and output via
PA, NA, PB and NB. A freely configurable zero signal
is simultaneously provided at pins PZ and NZ. The dif-
ferential RS422 line drivers are active; an Nx pin con-
stantly supplies a complementary signal which is the
inversion of pin Px.
Clock Down Pulse
Clock Up Pulse
Clock Pulse
NA
PB
NB
PZ
nU/D
MR
Count Direction (0: up, 1: down)
Asynch. Master Reset (active high)
Signal is ’1’ if index position is reached,
otherwise ’0’.
NZ
nPL
Asynch. Parallel Load Input (active low) /
Reset (active low)
Signal is ’0’ if index position is reached,
otherwise ’1’.
Table 14: Operating mode for counter devices compat-
ible with 74HC191 or 74HC193.
Mode 191/193
In Mode 191/193 the output pins provide control sig-
nals for counter devices compatible with 74HC191 or
74HC193 according to the following table. The driving
capability (SIK) and the slew rate (SSR) of the output Calibration 1, 2, 3
drivers must be selected so that the clock pulses can These modes are used to condition the input signals
be output with a low pulse of typically 50 ns (see Elec- and calibrate iC-MQ. In mode Calibration 1 the user
trical Characteristics, 511).
can measure the IBN bias current and the zero chan-
ICHAUS [ IC-HAUS GMBH ]
