iC-MH
12 BIT ANGULAR HALL ENCODER
Rev B1, Page 8/23
OVERVIEW
Adr
0x78
0x79
0x7A
0x7B
0x7C
0x7D
z
0x7E
0x7F
z
z
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Identification (0x78 bis 0x7B read-only)
Device ID - 0x4D (’M’)
Device ID - 0x48 (’H’)
Revision - 0x5A (’Z’)
Revision - 0x00 (”)
-
Manufacturer Revision - 0x00
Manufacturer ID - 0x00
Manufacturer ID - 0x00
z:
Register value programmable by zapping
p:
Register value write protected; can only be changed while V(VZAP)> Vt()hi
CFGTOS
Table 5: Register layout
Hall signal processing
. . . . . . . . . . . . . . . . . . . . Page 10
GAING:
GAINF:
GCC:
ENAC:
VOSS:
VOSC:
PRM:
CIBM:
DPU
HCLH
Hall signal amplification range
Hall signal amplification (1–20, log.
scale)
Amplification calibration cosine
Activation of amplitude control
Offset calibration sine
Offset calibration cosine
Energy-saving mode
Calibration of bias current
Deactivation of NERR pull-up
Activation of high Hall clock pulse
Sine/digital converter
. . . . . . . . . . . . . . . . . . . . . Page 16
CFGRES:
CFGZPOS:
CFGAB:
CFGPOLE:
CFGSU:
CFGMTD:
CFGDIR:
CFGHYS:
CFGCOM:
Test
TEST:
PROGZAP:
Resolution of sine digital converter
Zero point for position
Configuration of incremental output
No. of poles for commutation signals
Behavior during start-up
Frequency at AB
Rotating direction reversal
Hysteresis sine/digital converter
Zero point for commutation
RS422 driver
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 18
CFGDR:
TRIHL:
CFGO:
CFGPROT:
ENSSI:
Driver property
Tristate high-side/low-side driver
Configuration of output mode
Write/read protection memory
Activation of SSI mode
Test mode
Activation of programming routine
ICHAUS [ IC-HAUS GMBH ]
