iC-MH8
12 BIT ANGULAR HALL ENCODER
Rev A0.9, Page 22/25
The property of the RS422 driver of the connected line able a high transmission rate. A lower slew rate is of-
can be adjusted in the CFGDR register.
fered by the setting CFGDR = ’10’, which is excellent
for longer lines in an electromagnetically sensitive en-
vironment. Use of the setting CFGDR = ’11’ is advis-
able at medium transmission rates with a limited driver
capability.
CFGDR(1:0)
Addr. 0x05; bit 1:0
10 MHz 4 mA (default)
00
01
10
11
10 MHz 60 mA
300 kHz 60 mA
3 MHz 20 mA
TRIHL
00
Addr. 0x05; bit 3:2
Push Pull Output Stage
Highside Driver
Table 25: Driver property
01
10
Lowside Driver
11
Tristate
Signals with the highest frequency can be transmitted
in the setting CFGDR = ’00’. The driver capability is
at least 4 mA, however it is not designed for a 100 Ω
line. This mode is ideal for connection to a digital in-
Table 26: Tristate Register
put on the same assembly. With the setting CFGDR = The drivers consist of a push-pull stage in each case
’01’ the same transmission speed is available and the with low-side and high-side drivers which can each be
driver power is sufficient for the connection of a line activated individually. As a result, open-drain outputs
over a short distance. Steep edges on the output en- with an external pull-up resistor can also be realized.
Serial Interface
The serial interface is used to read out the absolute tailed description of the protocol, see separate inter-
position and to parameterize the module. For a de- face specification.
CDM
MA
SLI
Ack Start CDS D11 D10
D0
nE nW CRC5CRC4
Data Range
CRC0 Stop
Timeout
SLO
Figure 24: Serial Interface Protocol
Serial Interface
Protocol
Mode C
The sensor sends a fixed cycle-start sequence con-
taining the Acknowledge-, Start and Control-Bit fol-
lowed by the binary 12 bit sensor data. The low-active
error bit nE a ’0’ indicates an error which can be fur-
ther identified by reading the status register 0x77. The
following bit nW is always at ’1’ state. Following the
6 CRC bits the data of the next sensors, if available,
are presented. Otherwise, the master stops generat-
ing clock pulse on the MA line an the sensor runs into
a timeout, indicating the end of communication.
Cycle start sequence
Lenght of sensor data
CRC Polynom
Ack/Start/CDS
12 Bit + ERR + WARN
0b1000011
CRC Mode
inverted
Multi Cycle Data
max. Data Rate
not available
10 MHz
Table 27: Interface Protocol
ENSSI
Addr. 0x05; bit 7
Extended SSI-Mode
SSI-Mode
0
1
Table 28: Activation of SSI mode
The extended SSI-Mode is active if V(VZAP) = V()ZAP
or Bit ENSSI is 0. The extended SSI-Mode must be
ICHAUS [ IC-HAUS GMBH ]
