iC-MH8
12 BIT ANGULAR HALL ENCODER
Rev A0.9, Page 19/25
10°
0°
It should be noted then, however, that the maximum
rotation speed is reduced.
−10°
A
B
CFGDIR
Addr. 0x08; bit 5
Rotating direction CCW
Rotating direction CW
Z
0
1
0°
1.4°
0°
Figure 18: Quadrature signals for rotating direction
reversal (hysteresis 1.4°)
Table 20: Rotating direction reversal
At the reversal point at +10°, first the corresponding
edge is generated at A. As soon as an angle of 1.4°
has been exceeded in the other direction in accor-
dance with the hysteresis, the return edge is generated
at A again first. This means that all edges are shifted
by the same value in the rotating direction.
The rotating direction can easily be changed with
the bit CFGDIR. When the setting is CCW (counter-
clockwise, CFGDIR = ’0’) the resulting angular position
values will increase when rotation of the magnet is per-
formed as shown in figure 5. To obtain increasing an-
gular position values in the CW (clockwise) direction,
CFGDIR then has to be set to ’1’.
CFGZPOS(7:0)
Addr. 0x07; bit 7:0
0x0
0x1
0x2
...
0°
1,4°
2,8°
The internal analoge sine and cosine signal which are
available in test mode are not affected by the setting of
CFGDIR. They will always appear as shown in figure
5.
360
256 ·CFGZPOS
0xFF
358,6°
Table 18: Programming AB zero position
The position of the index pulse Z can be set in 1.4°
steps. An 8-bit register is provided for this purpose,
which can shift the Z-pulse once over 360°.
CFGSU
Addr. 0x08; bit 4
0
1
ABZ output "111" during startup
AB instantly counting to actual position
CFGMTD(2:0)
Addr. 0x06; bit 6:4
Table 21: Configuration of output startup
0
Minimum edge spacing 125 ns at IPO 1024 (max.
2 MHz at A)
1
2
Minimum edge spacing 250 ns at IPO 1024
Minimum edge spacing 500 ns at IPO 1024 (max.
500 kHz at A)
Depending on the application, a counter cannot bear
generated pulses while the module is being switched
on. When the supply voltage is being connected, first
the current position is determined. During this phase,
the quadrature outputs are constantly set to "111". In
the setting CFGSU = ’1’, edges are generated at the
output until the absolute position is reached. This en-
ables a detection of the absolute position with the in-
cremental interface.
3
4
5
6
7
Minimum edge spacing 1 µs at IPO 1024
Minimum edge spacing 2 µs at IPO 1024
Minimum edge spacing 4 µs at IPO 1024
Minimum edge spacing 8 µs at IPO 1024
Minimum edge spacing 16 µs at IPO 1024
Table 19: Minimum edge spacing
The CFGMTD register defines the time in which two
consecutive position events can be output at the high-
est resolution. The default is a maximum output fre- The converter for the generation of the commutation
quency of 500 kHz on A. This means that at the high- signals can be configured for two, four and eight-pole
est resolution, speeds of 30,000 rpms can still be cor- motors. Three rectangular signals each with a phase
rectly shown. In the setting with an edge spacing of shift of 120° are generated. With two-pole commuta-
125 ns, the edges can be generated even at the high- tion, the sequence repeats once per rotation. With a
est revolution and the maximum speed. However, the four-pole setting, the commutation sequence is gener-
counter connected to the module must be able to cor- ated twice per rotation. With a eight-pole setting, the
rectly process all edges in this case. The settings commutation sequence is generated four times per ro-
with 2 µs, and 8 µs can be used for slower counters. tation.
ICHAUS [ IC-HAUS GMBH ]
