iC-MH
12 BIT ANGULAR HALL ENCODER
Rev B1, Page 17/23
10°
0°
The rotating direction can easily be changed with
the bit CFGDIR. When the setting is CCW (counter-
clockwise, CFGDIR = ’0’) the resulting angular position
values will increase when rotation of the magnet is per-
formed as shown in figure 5. To obtain increasing an-
gular position values in the CW (clockwise) direction,
CFGDIR then has to be set to ’1’.
−10°
A
B
Z
0°
1.4°
0°
Figure 18: Quadrature signals for rotating direction
reversal (hysteresis 1.4°)
The internal analoge sine and cosine signal which are
available in test mode are not affected by the setting of
CFGDIR. They will always appear as shown in figure
5.
At the reversal point at +10°, first the corresponding
edge is generated at A. As soon as an angle of 1.4°
has been exceeded in the other direction in accor-
dance with the hysteresis, the return edge is generated
at A again first. This means that all edges are shifted
by the same value in the rotating direction.
CFGSU
Adr 0x08; Bit 3
0
1
ABZ output "111" during startup
AB instantly counting to actual position
Table 21: Configuration of output startup
CFGZPOS(7:0)
Adr 0x07; Bit 7:0
0x0
0x1
0x2
...
0°
Depending on the application, a counter cannot bear
generated pulses while the module is being switched
on. When the supply voltage is being connected, first
the current position is determined. During this phase,
the quadrature outputs are constantly set to "111" in
the setting CFGSU = ’0’. In the setting CFGSU = ’1’,
edges are generated at the output until the absolute
position is reached. This enables a detection of the
absolute position with the incremental interface.
1,4°
2,8°
360
256 ·CFGZPOS
0xff
358,6°
Table 18: Programming AB zero position
The position of the index pulse Z can be set in 1.4°
steps. An 8-bit register is provided for this purpose,
which can shift the Z-pulse once over 360°.
The converter for the generation of the commutation
signals can be configured for two and four-pole mo-
tors. Three rectangular signals each with a phase shift
of 120° are generated. With two-pole commutation, the
sequence repeats once per rotation. With a four-pole
setting, the commutation sequence is generated twice
per rotation.
CFGMTD2 CFGMTD
Minimum edge spacing
0
0
1
1
0
1
0
1
500 ns
125 ns
8 µs
max. 500 kHz at A
max. 2 MHz at A
max. 31.25 kHz at A
max. 125 kHz at A
2 µs
Table 19: Minimum edge spacing
CFGPOLE
Adr 0x8; Bit 1
2 pole commutation
4 pole commutation
0
1
The CFGMTB register defines the time in which two
consecutive position events can be output. The de-
fault is a maximum output frequency of 500 kHz on A.
This means that at the highest resolution, speeds of
30,000 rpms can still be correctly shown. In the set-
ting with an edge spacing of 125 ns, the edges can be
generated even at the highest revolution and the max-
imum speed. However, the counter connected to the
module must be able to correctly process all edges in
this case. The settings with 2 µs, and 8 µs can be used
for slower counters. It should be noted then, however,
that at higher resolutions the maximum rotation speed
is reduced.
Table 22: Commutation
The zero position of the commutation, i.e. the rising
edge of the track U, can be set as desired over a rota-
tion. Here 192 possible positions are available. Values
above 0xC0 are the mirrored positions from 0x70.
CFGPOLE(7:0)
Adr 0x09; Bit 7:0
0x00
0x01
...
0°
1,875°
360
192 · CFGCOM
CFGDIR
Adr 0x08; Bit 5
Rotating direction CCW
Rotating direction CW
0xBF
358,125°
0
1
Table 23: Commutation
Table 20: Rotating direction reversal
ICHAUS [ IC-HAUS GMBH ]
