iC-MH
12 BIT ANGULAR HALL ENCODER
Rev B1, Page 19/23
The property of the RS422 driver of the connected line enable a high transmission rate. A lower slew rate is
can be adjusted in the CFGDR register.
offered by the setting CFGDR = ’10’, which is excel-
lent for longer lines in an electromagnetically sensitive
environment. Use of the setting CFGDR = ’11’ is advis-
able at medium transmission rates with a limited driver
capability.
CfgDR(1:0)
Adr 0x07; Bit 1:0
10 MHz 4 mA (default)
10 MHz 60 mA
00
01
10
11
300 kHz 60 mA
3 MHz 20 mA
TRIHL
00
Adr 0x07; Bit 3:2
Push Pull Output Stage
Lowside Driver
Table 25: Driver property
01
10
Highside Driver
Tristate
11
Signals with the highest frequency can be transmitted
in the setting CFGDR = ’00’. The driver capability is
at least 4 mA, however it is not designed for a 100 Ω
line. This mode is ideal for connection to a digital in-
Table 26: Tristate Register
put on the same assembly. With the setting CFGDR The drivers consist of a push-pull stage in each case
= ’01’ the same transmission speed is available and with low-side and high-side drivers which can each be
the driver power is sufficient for the connection of a activated individually. As a result, open-drain outputs
line over a short distance. Steep edges on the output with an external pull-up resistor can also be realized.
Serial Interface
The serial interface is used to read out the absolute tailed description of the protocol, see separate inter-
position and to parameterize the module. For a de- face specification.
CDM
MA
SLI
Ack Start CDS D11 D10
D0
nE nW CRC5CRC4
Data Range
CRC0 Stop
Timeout
SLO
Figure 23: Serial Interface Protocol
Serial Interface
Protocol
Mode C
The sensor sends a fixed cycle-start sequence con-
taining the Acknowledge-, Start and Control-Bit fol-
lowed by the binary 12 bit sensor data. At lower resolu-
tion settings the data word contains leading zeros. The
low-active error bit nE a ’0’ indicates an error which
can be further identified by reading the status register
0x77. The following bit nW is always at ’1’ state. Fol-
lowing the 6 CRC bits the data of the next sensors, if
available, are presented. Otherwise, the master stops
generating clock pulse on the MA line an the sensor
runs into a timeout, indicating the end of communica-
tion.
Cycle start sequence
Lenght of sensor data
CRC Polynom
Ack/Start/CDS
12 Bit + ERR + WARN
0b1000011
CRC Mode
inverted
Multi Cycle Data
max. Data Rate
not available
10 MHz
Table 27: Interface Protocol
ENSSI
Adr 0x05; Bit 7
Extended SSI-Mode
SSI-Mode
0
1
Table 28: Activation of SSI mode
In the SSI mode the absolute position is output with 13
bits according to the SSI standard. However, in the SSI
ICHAUS [ IC-HAUS GMBH ]
