IC-LNG 参数 Datasheet PDF下载

iC-LNG

16-BIT OPTO ENCODER

preliminar y

Rev A1, Page 9/25

WITH SPI AND SERIAL / PARALLEL OUTPUTS

ELECTRICAL CHARACTERISTICS

Operating conditions: VDDA = 4 V to 5.5 V, VDD = 3 V to 5.5 V, GNDA = GND, Tj = -40°C to 125°C, unless otherwise specified.

Item

No.

901

902

903

904

905

Symbol

Parameter

Conditions

Min.

fin()

Vt()hi

Vt()lo

Vt()hys

Ipu()

Permissible Input Frequency at

SCK

Threshold Voltage hi at SCK, CS,

MOSI

Threshold Voltage lo at SCK, CS,

MOSI

Hysteresis at SCK, CS, MOSI

Pull-Up Current at SCK, MOSI

Vt() = Vt()hi - Vt()lo

V() = 0 V to VDD - 1 V

VDD = 3 V to 4 V

VDD = 4 V to 5.5 V

Vpu() = VDD - V(),

VDD = 3 V to 4 V, I() = -3 µA

VDD = 4 V to 5.5 V, I() = -5 µA

V() = 1 V . . . VDD

VDD = 3 V to 4 V

VDD = 4 V to 5.5 V

VDD = 3 V to 4 V, I() = 3 µA

VDD = 4 V to 5.5 V, I() = 5 µA

see Figure 2

30

30

5

8

25

60

0.8

40

-65

-120

100

-25

-60

-5

-10

400

Typ.

Max.

10

2

MHz

V

V

mV

µA

µA

mV

Unit

SPI Interface SCK, CS, MISO, MOSI

906

Vpu()

Pull-Up Voltage at SCK, MOSI

907

Ipd()

Pull-Down Current at CS

80

150

400

µA

µA

mV

ns

ns

908

909

910

Vpd()

t

CO

t

SO

Pull-Down Voltage at CS

Propagation Delay: MISO hi

after Falling Edge CS

Propagation Delay: MISO Stable see Figure 2

after Clock Edge SCK

Permissible Input Frequency at

CLK

Propagation Delay: DOUT

after Falling Edge NSL

see Figure 3

Shift Register CLK, NSL, DOUT, DIN

A01

A02

A03

A04

A05

A06

A07

fin()

t

NO

t

CO

Vt()hi

Vt()lo

Vt()hys

Ipu()

16

20

20

2

0.8

Vt() = Vt()hi - Vt()lo

V() = 0 V to VDD - 1 V

VDD = 3 V to 4 V

VDD = 4 V to 5.5 V

Vpu() = VDD-V(),

VDD = 3 V to 4 V, I() = -3 µA

VDD = 4 V to 5.5 V, I() = -5 µA

V() = 1 V to VDD

VDD = 3 V to 4 V

VDD = 4 V 5.5 V

VDD = 3 V to 4 V, I() = 3 µA

VDD = 4 V to 5.5 V, I() = 5 µA

5

8

25

60

40

-65

-120

100

-25

-60

-5

-10

400

MHz

ns

ns

V

V

mV

µA

µA

mV

Propagation Delay: DOUT stable see Figure 3

after Clock Edge CLK

Threshold Voltage hi at CLK,

NSL, DIN

Threshold Voltage lo at CLK,

NSL, DIN

Hysteresis at CLK, NSL, DIN

Pull-Up-Current at CLK, NSL

A08

Vpu()

Pull-Up-Voltage at CLK, NSL

A09

Ipd()

Pull-Down Current at DIN

80

150

400

µA

µA

mV

A10

Vpd()

Pull-Down-Voltage at DIN

Parallel Output Bit 0 to Bit 13 (Parameter EPG = 0x1)

B01 Vs()hi

Saturation Voltage hi

Vs()hi = VDD - V()

VDD = 3 V to 4 V, I() = 2.5 mA,

VDD = 4 V to 5.5 V, I() = 3.5 mA

B02

B03

B04

B05

B06

Isc()hi

Vs()lo

Isc()lo

tr()

tf()

Short-Circuit Current hi

Saturation Voltage lo

Short-Circuit Current lo

Rise Time

Fall Time

CL = 30 pF, V(): 10%

→

90% VDD

CL = 30 pF, V(): 90%

→

10% VDD

VDD = 3 V to 4 V, I() = 2.5 mA,

VDD = 4 V to 5.5 V, I() = 3.5 mA

4

-100

400

mV

-4

400

100

30

30

mA

mV

mA

ns

ns