iC-LNG 16-BIT OPTO ENCODER
WITH SPI AND SERIAL / PARALLEL OUTPUTS
Rev A1, Page 11/25
OPERATING CONDITIONS: Shift Register
Operating conditions: VDDA = 4 V to 5.5 V, VDD = 3 V to 5.5 V, GNDA = GND, Tj = -40°C to 125°C, unless otherwise specified.
Item Symbol
No.
Parameter
Conditions
Unit
Min.
1/fin(CLK)
30
Max.
I101 TCLK
I102 tNC
Permissible Clock Period
Setup Time:
ns
NSL lo before CLK lo → hi
I103 tNO
I104 tCO
I105 tIC
I106 tCI
I107 tNN
Propagation Delay:
(Elec. Char. No. A02)
DOUT stable after NSL hi → lo
Propagation Delay:
DOUT stable after Clock Edge CLK
(Elec. Char. No. A03)
Setup Time:
DIN stable before CLK lo → hi
Hold Time:
DIN stable after CLK lo → hi
Wait Time:
30
30
60
ns
ns
ns
between NSL lo → hi and NSL hi → lo
NSL
CLK
tNC
tNN
tNO
TCLK
DOUT
DIN
tNO
tCO
tIC tCI
Figure 3: Shift register timing
ICHAUS [ IC-HAUS GMBH ]
