iC-LNB 18-BIT OPTO ENCODER
WITH SPI AND SER/PAR INTERFACES
Rev A1, Page 15/35
OPERATING CONDITIONS: Shift Register
Operating conditions: VDDA = 4 V to 5.5 V, VDD = 3 V to 5.5 V, GNDA = GND, Tj = -40 °C to 125 °C, unless otherwise specified.
Item Symbol
No.
Parameter
Conditions
Unit
Min.
Max.
I101 TCLK
I102 tlo
Permissible Clock Period
see Elec. Char. No.: B05
1/fin()
Hold Time Load Signal:
30
ns
NSL low before NSL edge lo → hi
I103 tp3
I104 tp4
I105 tIC
I106 tCI
I107 thi
Propagation Delay:
Elec. Char. No.: B13
DOUT (idle state) after NSL lo → hi
Propagation Delay:
DOUT stable after clock edge CLK
Elec. Char. No.: B14
Setup Time:
DIN stable before CLK lo → hi
Hold Time:
DIN stable after CLK lo → hi
Preparation Time:
30
30
30
ns
ns
ns
NSL high before request of position
data (CLK hi → lo)
NSL
CLK
tlo
thi
tp3
TCLK
DOUT
DIN
tp4
tIC tCI
Figure 3: Shift register timing
ICHAUS [ IC-HAUS GMBH ]
