iC-LNB 18-BIT OPTO ENCODER
WITH SPI AND SER/PAR INTERFACES
Rev A1, Page 17/35
PROGRAMMING iC-LNB
REGISTER MAP (RAM)
Addr
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Signal calibration
0x00
0x01
0x02
0x03
0x04
0x05
P00
P01
P02
P03
P04
P05
0
GS(5:0)
GC(5:0)
LCMOD
OSP(6:0)
OSN(6:0)
OCP(6:0)
OCN(6:0)
LED power control
0x06 P06
Output configuration
LCTYP
NGRAY
LCSET(5:0)
0x07
0x08
P07
P08
DIR
EPG
OSZC(1:0)
GR(1:0)
SRC(2:0)
INC(2:0)
RNF
Test functions
0x09
P09
NENF
INVA
TA(1:0)
TMUX(3:0)
FlexCount
0x0A
P0A
P0B
P0C
P0D
P0E
P0F
P10
P11
HYS(6:0)
TRIABZ
0x0B
INVB
INVZ
Z90
SELABS
NENFLEX
HYS(7)
0x0C
ZPOS(6:0)
ZPOS(13:7)
0x0D
0x0E
RESIPO(1:0)
ZPOS(17:14)
0x0F
RESSUB(6:0)
RESSUB(13:7)
0x10
0x11
NOUTLO
0
STOPFLEX
0
ENIPO
0
RESSUB(17:14)
Status (read only)
0x12
0
0
ERRP
ERRS
POSOK
Table 6: Register layout
Address range
RAM monitoring (parity check)
The addresses of iC-LNB available through the SPI in- The configuration registers in the internal RAM are
terface range from addresses 0x00 to 0x12. As only constantly monitored by a parity check. Bit 7 of each
the lower five bits of the address byte are evaluated, address is the parity bit (P00-P11) and is supple-
with addresses that are greater than 0x1F the device mented to an even number of ones. The unused bits
returns to address range 0x00-0x12.
are also monitored. A parity error (internal ERRP) is
signaled at pin ERR (see the alarm output section).
ICHAUS [ IC-HAUS GMBH ]
