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IC-JXMQFP52 参数 Datasheet PDF下载

IC-JXMQFP52图片预览
型号: IC-JXMQFP52
PDF下载: 下载PDF文件 查看货源
内容描述: 16倍, 24 V与μC接口高侧驱动器 [16-FOLD 24 V HIGH-SIDE DRIVER WITH μC INTERFACE]
分类和应用: 驱动器
文件页数/大小: 36 页 / 603 K
品牌: ICHAUS [ IC-HAUS GMBH ]
 浏览型号IC-JXMQFP52的Datasheet PDF文件第12页浏览型号IC-JXMQFP52的Datasheet PDF文件第13页浏览型号IC-JXMQFP52的Datasheet PDF文件第14页浏览型号IC-JXMQFP52的Datasheet PDF文件第15页浏览型号IC-JXMQFP52的Datasheet PDF文件第17页浏览型号IC-JXMQFP52的Datasheet PDF文件第18页浏览型号IC-JXMQFP52的Datasheet PDF文件第19页浏览型号IC-JXMQFP52的Datasheet PDF文件第20页  
iC-JX  
16-FOLD 24 V HIGH-SIDE DRIVER WITH µC INTERFACE  
Rev C1, Page 16/36  
Interrupt Status Register A (read only)  
Adr. 0x04  
reset entry: 0x00  
Bit  
Name  
7
6
IET2  
5
IET1  
4
ISCI  
3
-
2
ET2  
1
ET1  
0
SCS  
DCHI  
Change-of-input data, overtemperatur, overcurrent (interrupts stored)  
Bit7  
DCHI  
Bit6  
IET2  
Bit5  
IET1  
Bit4  
0
1
0
1
0
1
0
1
No message  
Interrupt through change-of input message  
No message  
Interrupt through excessive temperature level 2  
No message  
Interrupt through excessive temperature level 1  
No message  
(r)  
(r)  
(r)  
(r)  
ISCI  
Interrupt through overcurrent message  
Excessive temperature status, overcurrent status (real time signals, at the time of readout)  
Bit2  
ET2  
Bit1  
ET1  
Bit0  
SCS  
0
1
0
1
0
1
No error message  
Excessive temperature level 2 (shutdown)  
No error message  
Excessive temperature level 1 (warning)  
No error message  
Overcurrent status (e.g. caused by low-side short circuit)  
(r)  
(r)  
(r)  
Interrupt Status Register B (read only)  
Adr. 0x05  
reset entry: 0x00  
0
Bit  
7
6
5
4
3
-
2
EOC  
1
USD  
Name  
IEOC  
ISD  
IUSD  
IUSA  
USA  
A/D-Converter, Bursts, Undervoltage (interrupts stored)  
Bit7  
IEOC  
Bit6  
ISD  
Bit5  
IUSD  
Bit4  
IUSA  
0
1
0
1
0
1
0
1
No message  
Interrupt by the A/D-Converter  
No message  
Interrupt caused by bursts at VDD  
No message  
Interrupt caused by undervoltage at VDD  
No message  
(r)  
(r)  
(r)  
(r)  
Interrupt caused by undervoltage at VCC  
A/D-Converter, Undervoltage (real time signals, at the time of readout)  
Bit2  
EOC  
Bit1  
USD  
Bit0  
USA  
0
1
0
1
0
1
No message  
A/D conversion completed (End of Conversion)  
No message  
Undervoltage at VDD  
No message  
Undervoltage at VCC  
(r)  
(r)  
(r)  
Read access gates off changes to the register; the register is reenabled only when reset via EOI. Any successive  
interrupts which occur at DCHI, IET2, IET1, ISCI, IEOC, ISD, IUSD und IUSA during the read-out phase and  
before a reset with EOI are trapped by an interrupt pipeline. If this happens, the message at NINT resp. D1/SOC  
or D2/SOB cannot be deletet by EOI, i.e. NINT resp. D1/SOC or D2/SOB constantly remains on low. In this  
instance, EOI fills the overcurrent message from the pipeline.  
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