iC-JRX
µP INTERFACE WITH 2×4 24V HIGH-SIDE DRIVERS
Rev A1, Page 7/23
Control Word 3
(flash pulse settings)
higher nibble
Bit
Name
7
NOBLFQ
6
NOCLK
5
PH1
4
PH0
lower nibble
3
-
2
-
1
PL1
0
PL0
Add.: 12
reset entry: 00h
higher nibble
Bit 7
NOBLFQ
Bit 6
NOCLK
Bit 5..4
PH1..0
0
1
0
1
Flash pulse is generated from the external clock signal at BLFQ
Flash Pulse is generated from clock signal CLK
Operation with the clock signal at CLK (all clock controlled actions are possible)
Operation without the clock signal at CLK (filtering etc. deactivated)
Flash frequency for I/O pins 4..7
PH1
0
0
1
1
PH0
0
1
0
1
NOBLFQ = 0
f(BLFQ)
f(BLFQ) / 2
f(BLFQ) / 4
f(BLFQ) / 16
NOBLFQ = 1
f(CLK) / 2
19
f(CLK) / 2
20
f(CLK) / 2
21
f(CLK) / 2
23
(r)
(r)
(r)
lower nibble
Bit 1..0
PL1..0
Flash frequency for I/O pins 0..3
PL1
0
0
1
1
PL0
0
1
0
1
NOBLFQ = 0
f(BLFQ)
f(BLFQ) / 2
f(BLFQ) / 4
f(BLFQ) / 16
NOBLFQ = 1
f(CLK) / 2
19
f(CLK) / 2
20
f(CLK) / 2
21
f(CLK) / 2
23
(r)
Control Word 4
(filter settings for overcurrent message)
Bit
Name
Bit 7
EOI
Add.: 13
reset entry: 00h
3
BYPSCF
2
-
1
-
0
SCFL
7
EOI
0
1
6
-
5
-
4
SCFH
No effect
(r)
"DELETE"s the interrupt message (change-of-input message; interrupt status register, overcurrent
message), accepts successive interrupts from the pipeline, deletes the message at INTN when the pipeline
is empty;
Bit automatically resets to '0'.
Bit 4
SCFH
0
1
Overcurrent message with 2.3ms filtering (higher nibble)
Overcurrent message with 4.6ms Filtering (higher nibble)
Gives the filter times with the maximum clock frequency permitted at CLK, i.e. 1.25 MHz:
2.3ms from (2689.5 ± 192)× t(CLK) and
4.6ms from (5378.5 ± 384) × t(CLK) respectively
(r)
Bit 3
BYPSCF
Bit 0
SCFL
0
1
0
1
Filters for the overcurrent message are active
Bypass for the filters: overcurrent messages are reprocessed in their unfiltered state
Overcurrent message with 2.3 ms filtering (lower nibble)
Overcurrent message with 4.6 ms filtering (lower nibble)
(r)
(r)
ICHAUS [ IC-HAUS GMBH ]
