Datasheet
DD2.X
PowerPC 750CL Microprocessor
Preliminary
5. System Design Information
This section provides electrical and thermal design recommendations for successful applications on the
750CL.
5.1 Reference Clock Selection
The PowerPC 750CL microprocessor supports either single-ended or differential clock inputs. The reference
clock is selected with the pin BVSEL. BVSEL set to GND selects a single-ended reference clock. BVSEL set
to OV selects differential clock inputs.
DD
For single-ended clock operation, the reference clock should be applied to pin SYSCLK. The pin SYSCLK
should be tied to GND.
For differential clock operation, the differential reference clocks should be applied to pin SYSCLK and
SYSCLK. The recommended board terminations are either:
• 50 Ω impedance to GND on pin SYSCLK and 50 Ω impedance to GND on pin SYSCLK or
• 100 Ω impedance between pins SYSCLK and SYSCLK
5.2 PLL Configuration
Table 5-1 shows the PLL configuration for the 750CL for nominal frequencies.
Table 5-1. 750CL Microprocessor PLL Configuration (Sheet 1 of 2)
PLL_CFG [0:4]
Processor to Bus Frequency Ratio
(PTBFR)
Binary
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
Decimal
4
5
2×
2.5×
3×
6
7
3.5×
4×
8
9
4.5×
5×
10
11
12
13
14
15
16
17
5.5×
6×
6.5×
7×
7.5×
8×
8.5×
Notes:
1. The SYSCLK frequency equals the core frequency divided by the processor-to-bus frequency ratio (PTBFR).
System Design Information
Page 44 of 70
Version 2.5
December 2, 2008
IBM [ IBM ]
