Datasheet
DD2.X
PowerPC 750CL Microprocessor
Preliminary
Table 4-1. Pinout Listing for the FCPBGA Package (Sheet 2 of 3)
Signal Name
Pin Number
Active
—
Input/Output
—
Notes
B2, B19, C5, C8, C13, C16, D10, D11, E3, E7, E14,
E18, F10, F11, G5, G8, G13, G16, H3, H8, H9, H12,
H13, H18, J12, K4, K7, K10, K14, K17, L4, L7, L10,
L14, L17, M12, N3, N8, N9, N12, N13, N18, P5, P8.
P13, P16, R10, R11, T3, T7, T14, T18, U10, U11, V5,
V8, V13,V16, W2, W19,
GND
HRESET
INT
Y11
Y9
Low
Low
—
Input
Input
—
KGND
KVDD
Y1
9
9
Y2
—
—
L1_TSTCLK
L2_TSTCLK
LSSD_MODE
MCP
Y13
W13
U13
W12
High
High
Low
Low
Input
Input
Input
Input
8
10
1
U14, Y4, D16, D13, A13, B8, T20, N19, J20, G19, B1,
G4, H1, M1, A10, W8
NB
—
—
—
—
5
2
C4, C7, C14, C17, D3, D18, E10, E11, G3, G7, G14,
G18, H5, H16, K5, K16, L5, L16, N5, N16, P3, P7, P14,
P18, T10, T11, U3, U18, V4, V7, V14, V17
OVDD
PLL_CFG[0:4]
QACK
QREQ
SMI
Y18, W17, Y17, U16, W14
High
Low
Low
Low
Low
High
Low
Low
Low
High
High
High
Input
Input
Y8
U8
Output
Input
W10
Y7
SRESET
SYSCLK
SYSCLK
TA
Input
W16
W15
A12
A11
T2
Input
6
6
Input
Input
TBST
Input/Output
Input
TCK
4
TDI
V2
Input
TDO
W5
Output
Notes:
1. These are test signals for factory use only and must be pulled up to OVDD for normal machine operation.
2. OVDD inputs supply power to the input/output drivers and VDD inputs supply power to the processor core.
3. BVSEL low selects single-ended clock input on SYSCLK. BVSEL high selects differential clock input on SYSCLK and SYSCLK.
4. TCK must be tied high or low for normal machine operation.
5. No ball is installed in this location.
6. SYSCLK is the active low clock input used with SYSCLK in differential mode. In single-ended mode, SYSCLK is used as the clock
input, and SYSCLK is grounded.
7. Must be connected to OVDD during normal operation.
8. Must be connected to GND during normal operation.
9. Kelvin VDD and GND for voltage regulator sensing.
10. On DD1.x, this signal must be pulled up to OVDD for normal operation. On DD2.x, this signal selects the I/O operating voltage such
that a pulldown to GND selects 1.8 V and a pull up to OVDD selects 1.15 V.
Dimensions and Signal Assignments
Page 42 of 70
Version 2.5
December 2, 2008
IBM [ IBM ]
