Datasheet
DD2.X
Preliminary
PowerPC 750CL Microprocessor
Table 4-1. Pinout Listing for the FCPBGA Package (Sheet 3 of 3)
Signal Name
Pin Number
Active
Low
Input/Output
Input
Notes
TEA
W6
THRMD1
THRMD2
M6
See Section 5.6 on page 48
J6
TLBISYNC
TMS
W11
Low
Input
Input
V1
High
Low
Low
High
High
TRST
U1
Input
TS
B15
Input/Output
Output
TSIZ[0:2]
TT[0:4]
A14, B12, B11
D14, B17, B14, A15, B13
Input/Output
C10, C11, E8, E13, F6, F9, F12, F15, J8, J9, J13, K3,
K8, K11, K13, K18, L3, L8, L11, L13, L18, M8, M9,
M13, R6, R9, R12, R15, T8, T13, V10, V11
VDD
—
—
2
WT
U5
Low
Output
Notes:
1. These are test signals for factory use only and must be pulled up to OVDD for normal machine operation.
2. OVDD inputs supply power to the input/output drivers and VDD inputs supply power to the processor core.
3. BVSEL low selects single-ended clock input on SYSCLK. BVSEL high selects differential clock input on SYSCLK and SYSCLK.
4. TCK must be tied high or low for normal machine operation.
5. No ball is installed in this location.
6. SYSCLK is the active low clock input used with SYSCLK in differential mode. In single-ended mode, SYSCLK is used as the clock
input, and SYSCLK is grounded.
7. Must be connected to OVDD during normal operation.
8. Must be connected to GND during normal operation.
9. Kelvin VDD and GND for voltage regulator sensing.
10. On DD1.x, this signal must be pulled up to OVDD for normal operation. On DD2.x, this signal selects the I/O operating voltage such
that a pulldown to GND selects 1.8 V and a pull up to OVDD selects 1.15 V.
Version 2.5
Dimensions and Signal Assignments
Page 43 of 70
December 2, 2008
IBM [ IBM ]
