Datasheet
DD2.X
PowerPC 750CL Microprocessor
Preliminary
5.4 Decoupling Recommendations
Capacitor decoupling is required for the 750CL. Decoupling capacitors act to reduce high-frequency chip
switching noise and provide localized bulk charge storage to reduce major power-surge effects. Guidelines
for high-frequency noise decoupling will be provided in a separate application note. Bulk decoupling requires
a more complete understanding of the system and system power architecture, which is beyond the scope of
this document.
High-frequency decoupling capacitors should be located as close as possible to the processor with low lead
inductance to the ground and voltage planes.
Decoupling capacitors are recommended on the back of the card, directly opposite the module. The recom-
mended placement and number of decoupling capacitors, 34 V -GND capacitors and 44 OV -GND
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capacitors, are described in Figure 5-2 on page 47. The recommended decoupling capacitor specifications
are provided in Table 5-2. The placement and usage described here are guidelines for decoupling capacitors
and should be applied for system designs.
Table 5-2. Recommended Decoupling Capacitor Specifications
Item
Description
Type X5R or Y5V
10 V minimum
0402 size
Decoupling capacitor specifications
40 × 20 mils, nominally
1.0 mm × 0.5 mm ±0.1 mm on both dimensions
100 nF
34 VDD-GND capacitors
44 OVDD-GND capacitors
Recommended minimum number of decou-
pling capacitors on the back of the card
Note: The decoupling capacitor electrodes are located directly opposite their corresponding BGA pins where
possible. Also, each electrode for each decoupling capacitor needs to be connected to one or more BGA pins
(balls) with a short electrical path. Thus, through-vias adjacent to the decoupling capacitors are recom-
mended.
The card designer can expand on the decoupling capacitor recommendations by doing the following:
• Adding additional decoupling capacitors.
If using additional decoupling capacitors, verify that these additional capacitors do not reduce the number
of card vias or cause the vias to lose proximity to each capacitor electrode.
• Adding additional through-vias or blind-vias.
Card technologies are available that will reduce the inductance between the decoupling capacitor and the
BGA pin (ball). Replacing single vias with multiple vias is highly recommended. Place GND vias close to
V
or OV vias to reduce loop inductance.
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Figure 5-2 on page 47 shows the mapping of power, ground, and signal pin assignments, and the recom-
mended layout of decoupling capacitors under application conditions. In test mode, pins C11 and G8 can be
used as Kelvin probes, in which case the pins should be disconnected from card GND and V . Capacitors
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should not be connected to the Kelvin pins during Kelvin probe voltage measurements.
System Design Information
Page 46 of 70
Version 2.5
December 2, 2008
IBM [ IBM ]
