Preliminary
IBMN312804CT3
IBMN312404CT3
128Mb Synchronous DRAM - Die Revision B
IBMN312164CT3
Mode Register Operation (Address Input For Mode Set)
BS1 BS0 A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Address
Bus (Ax)
Operation Mode
CAS Latency
BT
Burst Length
Mode
Register(Mx)
Burst Type
M3
0
1
Type
Sequential
Interleave
Operation Mode
M13 M12 M11 M10 M9
0
0
0
0
0
0
0
0
0
1
M8
0
0
M7
0
0
Mode
Normal
Multiple Burst
with
Single Write
Burst Length
Length
M2
0
0
0
M1
0
0
1
1
0
0
1
1
M0
Sequential Interleave
0
1
0
1
0
1
0
1
1
2
4
8
Reserved
Reserved
Reserved
Reserved
1
2
4
8
Reserved
Reserved
Reserved
Reserved
CAS Latency
M6
0
0
0
0
1
1
1
1
M5
0
0
1
1
0
0
1
1
M4
0
1
0
1
0
1
0
1
Latency
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
0
1
1
1
1
06K7582.H03335A
01/01
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
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