IBMN312164CT3
IBMN312804CT3
IBMN312404CT3
Preliminary
128Mb Synchronous DRAM - Die Revision B
Burst Read Command
The Burst Read command is initiated by having CS and CAS low while holding RAS and WE high at the rising
edge of the clock. The address inputs determine the starting column address for the burst, the Mode Register
sets the type of burst (sequential or interleave) and the burst length (1, 2, 4, 8). The delay from the start of the
command to when the data from the first cell appears on the outputs is equal to the value of the CAS latency
that is set in the Mode Register.
Burst Read Operation
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
CAS latency = 2
DOUT A
DOUT A
DOUT A
DOUT A
DOUT A
DOUT A
DOUT A
0
1
2
3
tCK2, DQs
CAS latency = 3
DOUT A
3
0
1
2
tCK3, DQs
Read Interrupted by a Read
A Burst Read may be interrupted before completion of the burst by another Read Command, with the only
restriction being that the interval that separates the commands must be at least one clock cycle. When the
previous burst is interrupted, the remaining addresses are overridden by the new address with the full burst
length. The data from the first Read Command continues to appear on the outputs until the CAS latency from
the interrupting Read Command is satisfied, at this point the data from the interrupting Read Command
appears.
Read Interrupted by a Read
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK
READ A
READ B
NOP
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
CAS latency = 2
DOUT A
DOUT B
DOUT A
DOUT B
DOUT B
DOUT B
3
0
0
0
1
2
tCK2, DQs
CAS latency = 3
DOUT B
DOUT B
DOUT B
DOUT B
3
0
1
2
tCK3, DQs
©IBM Corporation. All rights reserved.
06K7582.H03335A
01/01
Use is further subject to the provisions at the end of this document.
Page 11 of 66
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