IBM13N8644HCC
IBM13N8734HCC
8M x 64/72 One-Bank Unbuffered SDRAM Module
Refresh Cycle
-260
-360
-10
Symbol
Parameter
Units Notes
Min.
—
Max.
64
Min.
—
Max.
64
Min.
—
Max.
64
t
1
Refresh Period
Self Refresh Exit Time
ms
ns
REF
t
10
10
10
SREX
1. 4096 auto refresh cycles.
Write Cycle
-260
-360
-10
Symbol
Parameter
Units
Min.
Max.
Min.
2
Max.
—
Min.
3
Max.
t
Data In Set-up Time
Data In Hold Time
2
1
—
—
—
—
—
—
ns
ns
ns
DS
t
1
—
1
DH
t
Data input to Precharge
15
15
—
15
DPL
Data In to Active Delay
CAS Latency = 2
t
5
—
5
—
5
—
CLK
DAL2
Data In to Active Delay
CAS Latency = 3
t
4
0
—
—
4
0
—
—
4
0
—
—
CLK
CLK
DAL3
t
DQM Write Mask Latency
DQW
Presence Detect Read and Write Cycle
Symbol
Parameter
Min.
Max.
Units
kHZ
ns
Notes
f
SCL Clock Frequency
100
100
3.5
SCL
T
Noise Suppression Time Constant at SCL, SDA Inputs
SCL Low to SDA Data Out Valid
I
t
0.3
4.7
4.0
4.7
4.0
4.7
0
µs
AA
t
Time the Bus Must Be Free before a New Transmission Can Start
Start Condition Hold Time
Clock Low Period
µs
BUF
t
µs
HD:STA
t
µs
LOW
t
Clock High Period
µs
HIGH
t
Start Condition Setup Time (for a Repeated Start Condition)
Data in Hold Time
µs
SU:STA
t
µs
HD:DAT
t
Data in Setup Time
250
ns
SU:DAT
t
SDA and SCL Rise Time
1
µs
r
t
SDA and SCL Fall Time
300
ns
f
t
Stop Condition Setup Time
Data Out Hold Time
4.7
µs
SU:STO
t
300
ns
DH
t
1
Write Cycle Time
15
ms
WR
1. The Write cycle time (t ) is the time from a valid stop condition of a write sequence to the end of the internal Erase/Program
WR
cycle. During the Write cycle, the bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resis-
tor, and the device does not respond to its slave address.
19L7295.E93875B
12/99
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 15 of 19
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