IBM13N8644HCC
IBM13N8734HCC
8M x 64/72 One-Bank Unbuffered SDRAM Module
Common Parameters
-260
-360
-10
Sym-
bol
Parameter
Units Notes
Min.
Max.
—
Min.
2
Max.
—
Min.
3
Max.
—
t
t
Command Setup Time
Command Hold Time
2
1
ns
ns
ns
ns
CS
—
1
—
1
—
CH
t
Address and Bank Select Set-up Time
Address and Bank Select Hold Time
RAS to CAS Delay
2
—
2
—
3
—
AS
t
1
—
1
—
1
—
AH
t
1
1
1
1
1
20
70
50
20
20
1
—
20
70
50
20
20
1
—
30
90
60
30
20
1
—
ns
ns
RCD
t
Bank Cycle Time
—
—
—
RC
t
Active Command Period
Precharge Time
100000
—
100000
—
100000
—
ns
RAS
t
ns
RP
t
Bank to Bank Delay Time
CAS to CAS Delay Time
—
—
—
ns
RRD
CCD
t
—
—
—
CLK
1. These parameters account for the number of clock cycle and depend on the operating frequency of the clock, as follows:
the number of clock cycles = specified value of timing / clock period (count fractions as a whole number).
Mode Register Set Cycle
-260)
-360
-10
Symbol
Parameter
Units Notes
Min.
2
Max.
—
Min.
2
Max.
—
Min.
2
Max.
—
t
1
Mode Register Set Cycle Time
clk
RSC
1. These parameters account for the number of clock cycle and depend on the operating frequency of the clock, as follows:
the number of clock cycles = specified value of timing / clock period (count fractions as a whole number).
Read Cycle
-260
-360
-10
Symbol
Parameter
Units Notes
Min.
2.5
3
Max.
—
Min.
2.5
3
Max.
—
Min.
2.5
3
Max.
—
2
3
ns
ns
ns
t
Data Out Hold Time
OH
—
t
Data Out to Low Impedance Time
Data Out to High Impedance Time
Data Out to High Impedance Time
DQM Data Out Disable Latency
0
—
0
—
6
0
—
7
LZ
t
1
1
1
3
3
2
6
6
3
3
2
3
3
2
ns
ns
HZ3
t
8
8
HZ2
t
—
—
—
CLK
DQZ
1. Referenced to the time at which the output achieves the open circuit condition, not to output voltage levels.
2. AC Output Load Circuit A.
3. AC Output Load Circuit B.
19L7295.E93875B
12/99
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 14 of 19
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