IBM13N8644HCC
IBM13N8734HCC
8M x 64/72 One-Bank Unbuffered SDRAM Module
AC Characteristics (TA= 0 to +70°C, VDD= 3.3V ± 0.3V)
1. An initial pause of 200µs, with DQMB0-7 and CKE0 held high, is required after power-up. A Precharge All
Banks command must be given followed by a minimum of eight Auto (CBR) Refresh cycles before or after
the Mode Register Set operation.
2. The Transition time is measured between V and V (or between V and V ).
IH
IL
IL
IH
3. In addition to meeting the transition rate specification, the CK0, CK2, and CKE0 signals must transit
between V and V (or between V and V ) in a monotonic manner.
IH
IL
IL
IH
4. Load Circuit A: AC timing tests have V = 0.4 V and V = 2.4 V with the timing referenced to the 1.40V
IL
IH
crossover point.
5. Load Circuit A: AC measurements assume t =1.0 ns.
T
6. Load Circuit B: AC timing tests have V = 0.8 V and V = 2.0 V with the timing referenced to the 1.40V
IL
IH
crossover point.
7. Load Circuit B: AC measurements assume t =1.2 ns.
T
AC Characteristics Diagrams
t
T
Vtt=1.4V
t
CKH
V
IH
50Ω
Output
1.4V
VIL
Clock
Input
t
CKL
Zo = 50Ω
50pF
t
SETUP
AC Output Load Circuit (A)
t
HOLD
1.4V
Output
Zo = 50Ω
t
OH
t
AC
50pF
t
LZ
AC Output Load Circuit (B)
1.4V
Output
19L7295.E93875B
12/99
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 12 of 19
IBM [ IBM ]
