IBM39STB032xx
IBM39STB034xx
STB032xx and STB034xx Digital Set-Top Box Integrated Controllers
Preliminary
SDRAM Controller
The SDRAM Controller transfers data between the PLB and up to two SDRAM memory banks attached to the
external bus. The Controller implements address and data pipelining and supports 16Mb and 64Mb SDRAMS
concurrently. It also provides the following:
• Direct-connect SDRAM interface
• High bandwidth with a narrow 16-bit interface
• Page interleaving
• Programmable address select
• Programmable rates for automatic SDRAM refresh
• Software-initiated and self refresh modes for power savings
Crossbar Switch
The PLB Crossbar Switch (CBS) creates a flat memory model and implements Unified Memory Architecture
(UMA), which connects multiple PLB master buses to multiple PLB slave buses, thus allowing two sets of
PLB buses to intercommunicate. Processor, transport, and the audio and video decoders can access mem-
ory through either memory controller.
Digital Audio/Video Subsystem
The MPEG-2 Digital Audio/Video subsystem provides fully-synchronized playback of digital video and audio
programs, with a minimum of interaction from the PPC405B3 processor.
Audio PLL
DVB Descrambler
MPEG-2 Transport
MPEG-2
Dolby Digital
Audio Decoder
to Audio D/A and IEC60958
MPEG-2
Video
Decoder
OSD
DENC
PLB0
MPEG-2 Video Decoder with OSD
The MPEG-2 video decoder provides decompression, decoding, and synchronized playback of digital video
streams with a minimum of host support. It produces interlaced video output and can support MPEG-2 com-
pressed data streams up to an average rate of 15 Mbps. The video decoder is also backward compatible to
support the ISO/IEC International Standard 11172-2 (11/93) (also called “MPEG-1 Standard”). It supports the
ISO/IEC 13818-2 Main Profile at Main Level.
Architecture and Subsystem Information
Page 8 of 55
STB03_sds_041800.fm.01
April 18, 2000
IBM [ IBM ]
