IBM39STB032xx
IBM39STB034xx
STB032xx and STB034xx Digital Set-Top Box Integrated Controllers
Preliminary
On-chip instruction is compatible with PowerPC User Instruction Set Architecture, with branch prediction exe-
cution for most instructions. There are 32 x 32 bit general purpose registers. Instruction and data cache
arrays improve system throughput. The CPU has a separate two-way set-associative 16KB instruction cache
and an 8KB write-back/write-through data cache. Multiply and divide instructions are performed in hardware
and are not emulated in software.
Universal Interrupt Controller
The Universal Interrupt Controller (UIC) provides all necessary control, status, and communication functions
between all sources of interrupts and the PPC405B3. The UIC combines STB03xxx interrupts and presents
them to the PPC405B3’s critical or non-critical inputs. All interrupts can be programmed to generate either
critical or non-critical output. Interrupts can be level- or edge-sensitive and interrupt polarity is programmable.
An optional read-only vector is used to reduce critical interrupt servicing latency. This vector is generated by
combining an offset (based on the bit position of the highest priority, enabled, and active critical interrupt) and
a vector base address register. A configurable priority control bit determines whether the least significant or
most significant bit in the status register has the highest priority.
Clock and Power Management
For power-saving purposes, a Clock and Power Management (CPM) input is used to shut down clocks and
device functions. A reset is required to activate a unit.
Memory Interface Subsystem
The memory interface subsystem provides the system memory controller interface for SRAM, FLASH Mem-
ory, ROM, and SDRAM. It also provides the Direct Memory Access (DMA) interfaces for these memories. A
key advantage of the memory interface is its ability to gain concurrent access (one function to SDRAM0 and
one function to SDRAM1) and mutual access (a given function can access either port).
Memory Subsystem
FLASH,
DMA
EBIU
ROM, etc.
SDRAM
PLB0
PLB1
EBIU
SDRAM0
SDRAM
SDRAM1
Direct Memory Access Controller
The four-channel DMA controller is a processor local bus master that allows faster data transfer between
memory and peripherals than with program control. The controller supports memory-to-memory, peripheral-
to-memory, and memory-to-peripheral transfers. The DMA controller allows the PPC405B3 processor to exe-
cute instructions with no bus contention when the PPC405B3 is executing from cache. DMA is useful when
Architecture and Subsystem Information
Page 6 of 55
STB03_sds_041800.fm.01
April 18, 2000
IBM [ IBM ]
